FAQ for FR Family

CPU

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1. What is the difference between RAMs connected to D-Bus and C-Bus? (Target: MB91126)
2. What is SSP (system stack)?
3. Is there any constraint for setting the stack pointer?
4. For the restore factor from the stop mode, not only the interrupt factor but also the interrupt enabled factor is required?
5. Downloading a program to the internal RAM on ICE and then executing the program causes unknown operations (operation different from the disassembling of RAM). Is it impossible to use the internal RAM as a program area? (Target: MB91101)
6. Can we set a little endian area? (Target: MB91101)
7. In area 0, the program memory is allocated. Is it no problem to access the program memory during a the setup of area 0? (Target: MB91301)
8. It is described that the setting areas should not be overlapped, but area 0 has been set to whole by reset. Is it necessary to first set area 0 and then set the other areas? (Target: MB91301)
9. How many bits is the bus width for reading the mode vector? (Target: MB91301)
10. How is the internal 32-bit data written to the 16-bit width external bus? (Target: MB91F155)
11. Is it possible to enter a program routine into a cache and keep it inside the cache? (Target: MB91101, MB91301, MB91307)
12. What are the stepwise division flag and stepwise trace trap flag?
13. How is the interlock function used?

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What is the difference between RAMs connected to D-Bus and C-Bus? (Target: MB91126)

• Answer :
  RAM connected to D-Bus: Data RAM area
  RAM connected to C-Bus: Available for both instruction execution and data RAM area.

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What is SSP (system stack)?

• Answer :
  Register R15 indicates the stack pointer that is effective at the time. There are two stack pointers, SSP and USP, of which the effective stack pointer is referenced as R15. Which is to be used is determined by the S flag of the PS register. The initial value is SSP. SSP is used as the stack pointer at interrupt. USP can also be used by user applications.

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Is there any constraint for setting the stack pointer?

• Answer :
  Specify an address of a multiple of 4, since word access is performed to the stack.

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For the restore factor from the stop mode, not only the interrupt factor but also the interrupt enabled factor is required?

• Answer :
  To restore from the stop mode, the interrupt should be enabled to jump to the interrupt routine.

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Downloading a program to the internal RAM on ICE and then executing the program causes unknown operations (operation different from the disassembling of RAM). Is it impossible to use the internal RAM as a program area? (Target: MB91101)

• Answer :
  Since the DATA bus is connected to the internal RAM （0x1000 to 0x17FF）, use it as the RAM for DATA.

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Can we set a little endian area? (Target: MB91101)

• Answer :
  One of areas 1 to 5 can be used as a little endian area by specification of the Little Endian Register (0x7FE).

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In area 0, the program memory is allocated. Is it no problem to access the program memory during a the setup of area 0? (Target: MB91301)

• Answer :
  Access is possible but make sure that the area where the program being executed exists is not out of the CS0 area. After reset, at the first write to ACR0, the whole area specification is canceled and area 0 is set into the specified size.

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It is described that the setting areas should not be overlapped, but area 0 has been set to whole by reset. Is it necessary to first set area 0 and then set the other areas? (Target: MB91301)

• Answer :
  At first, set area 0. Then set the other areas in the not overlapped space. In advance, it is necessary to specify the bus width for area 0 by the mode vector （0xFFFF8）.

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How many bits is the bus width for reading the mode vector? (Target: MB91301)

• Answer :
  The mode vector is 8-bit data allocated at 0xFFFF8 and accessed via 8-bit bus. Any bus width is set to the minimum bus width that allows the memory access.

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How is the internal 32-bit data written to the 16-bit width external bus? (Target: MB91F155)

• Answer :
  For performing 32-bit width data access for the external bus, the data is divided into 16 bits × 2.

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Is it possible to enter a program routine into a cache and keep it inside the cache? (Target: MB91101, MB91301, MB91307)

• Answer :
  Set the enable-bit of the cache in advance.
  
  1. Set the EOLK bit to "1."
  2. Execute the function to be locked.
  3. Clear the EOLK bit back to "0."
  By this means, the execution program can be locked.

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What are the stepwise division flag and stepwise trace trap flag?

• Answer :
  The stepwise division flag is a register for storing the result during stepwise division operation, so do not write into it. The stepwise trace trap flag is a flag to be used by the tool, so do not manipulate it.

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How is the interlock function used?

• Answer :
  Interlock may occur when the accessing register has been used by the immediately previous instruction. The Softune assembler automatically performs optimization so as not to cause an interlock.