Tell us the number of cycles to be used when accessing the following memory: 1) Built-in data RAM (D bus) 2) Built-in instruction
RAM (F bus) Under the following condition, how long does accessing external memory take in comparison with accessing built-in
data RAM/built-in instruction RAM?（Target: FR60/ FR60lite)
Answer : For FR60/FR60lite, the number of access cycles from time when an access is executed on the memory stage to time when it is
actually read is
built-in data RAM (D bus): one cycle and
built-in instruction RAM (F bus): two cycles.
The number of cycles for external memory is two, being the same as 2) above. For your reference, the following shows access
cycles to each bus:
R-Bus series: About eight clock cycles (CLKB:CLKP =1:1) About 13 clock cycles (CLKB:CLKP =1:1/2)
T-Bus series: About six clock cycles (CLKB:CLKT = 1:1) About eight clock cycles (CLKB:CLKT =1:1/2)
Interrupt operation (rewriting the "I" flag of PS/accessing registers in CPU): one clock cycle Instruction cache control (Harvard bus connection module): one clock cycle
When the internal ROM and RAM are accessed, ADDR, RD, and WR0/WR1 are output?Are these control signals output only when the
external areas are accessed? (Target: MB91F155A)
Answer : For the ADDR signal, the address signal for the immediately previous external bus access is held and continuously output.The
CS signal is also output. However, neither RD nor WR0/WR1 is output.
How many CPU cycles is in the number of external bus cycles? (Target: MB91360)
Answer : An external bus cycle normally (without wait) takes four CPU cycles (bus converter *two cycles + external bus interface *two
cycles = four cycles).
We consider placing a program onto the external Flash. How much is the performance degraded in comparison with the internal
Flash? (Target: MB91350)
Answer : The answer to this question heavily depends on the instructions (such as prefetch). However, use internal:external (non-wait)
= 1:3 as a guide for the consideration.
