I want to know a data sampling method for UART error tolerance.
Answer : When UART baud rate operates on an internal clock, eight internal clocks constitute one bit. For the start-bit, sampling is
performed with the first four internal clocks. For the data-bit, sampling is performed once with the central internal clock.
When UART baud rate is generated from external clocks, 16 internal clocks constitute one bit.
I want to know how the start bit is accepted and detected.
Answer : The UART start bit is detected at a low level. The UART start bit is accepted as the start bit when the pin retains the low
levels of eight UART operating clocks (baud rate clock 1/16) after a low level is detected. However, when a high level is
detected at the pin before the UART start bit is accepted, the UART start bit is not accepted as the start bit. Start bit
redetection is started from the succeeding low level of the pin.
Is it possible to transmit and receive 9-bit data?
Answer : In multiprocessor mode, the A/D bit can be used to transmit 9-bit data but cannot be used to receive 9-bit data. However,
a method for checking a parity error by using a parity with software is available. MB90590 and MB90390 can transmit and receive
9-bit data because they provide the D9 bit. (Respondent:Fujitsuka)
I want to know how to calculate baud rate when using an internal timer (PPG).
Answer : Asynchronous communication (asynchronous) : (1/16) × 1/(PPG set cycle) CLK synchronization : 1/(PPG set cycle) Relationship
between each PPG mode and UART baud rate clock sources
8bit-PPG 2ch independent mode The PPG set cycle ("H" level + "L" level) is used as a baud rate clock source.
16bit-PPG mode The cycle ("H" level + "L" level) set after PPG 0ch and PPG 1ch have been concatenated is used as a baud rate clock
source.
8bit prescaler + 8bit-PPG 1ch mode The set cycle ("H" level + "L" level) on the PPG 1ch side is used as a baud rate clock source. The set cycle on the
PPG 0ch side is used as a PPG 1ch count clock.
I want to set UART transfer rate in a timer. Which timer (PPG0 or PPG1) do you recommend? (Target:MB90570series)
Answer : PPG is used when transfer rate is set in a UART timer. Set UART0/1 in PPG1. (Two output pins (PPG0 and PPG1) are available
but output is not enabled even if PPG0 is set.)
If reception operation is performed with a built-in baud rate generator, 2-byte data is received, not 1-byte data (16 reception
clocks are continuously output). Why?
Answer : If the built-in baud rate generator is used, data is written to the SODR register to perform reception operation. Therefore,
confirm whether data is written to the SODR register other than reception operation, including cases such as "before transmission
is enabled."
What is the maximum frequency of an SIO/UART external input clock?
Answer :The maximum frequency of the SIO/UART external input clock depends on devices, so see the UART/SIO timing of each
device data sheet. (In most cases, the maximum frequency is 8 tcp. The maximum frequency is obtained by dividing the internal
operating frequency by 8.)
When UART reception operation (RXE=0) is disabled during UART reception, what happens?
Answer :When UART reception operation (RXE=0) is disabled during UART reception, UART reception stops after the reception
of the data being received has been completed.
When UART transmission operation is disabled (TXE=0) during UART transmission, what happens?
Answer : When UART transmission operation is disabled (TXE=0) during UART transmission, UART transmission stops after data in the SODR
register has been transmitted.
When UART is used with the clock synchronous SIO and a clock is input externally, if the shift clock being received stops,
what happens?
Answer : When UART is used with the clock synchronous SIO and a clock is input externally, if the shift clock being received may stop,
the internal shift clock also stops and remains in this status till the next clock is input. When you want to restart UART
without the reset bit from bit 0 because UART does not have the reset bit, it is necessary to input remaining clocks from
the port. This is because a method for clearing the shift clock counter is unavailable.
Can data reception and data transmission operate separately in clock synchronous mode?
Answer : In clock synchronous mode, data transmission and data reception operate at the same time. For this reason, when you want to
perform only reception operation, you should disable the transmission pin.
I want to know operation when the UART communication line performs GND bite (when the RX pin of the CPU is the "LOW" fixed
status). Is the error flag set many times during GND bite even if the error flag is cleared? Or is the error flag reflected
only when the falling edge of the start bit is detected?
Answer : When the RX pin of UART is in "LOW" short status, the UART macro outputs a framing error. This error should be cleared
by using "IO_UMC0.bit.RFC." After this RFC is cleared, the framing error is cleared but the RX pin is kept at "LOW."
When the start bit is detected again, UART is restarted. After UART is started, the framing error is reoutput to cause an
interrupt according to the timing of the STOP bit.
The manual mentions that dummy transmission data should be written to the SODR1 register even if data is only received in
the CLK synchronous mode. Why?
Answer : In CLK synchronous mode, Writing dummy data to the SODR1 register makes it possible to receive 8-bit data. In this case, both
internal clocks and external clocks require that dummy data be written. To receive data continuously, dummy data should be
written each time 8-bit data is received. (When data is received, data is output from the sending pin.)
The manual mentions that the reset value of TDRE is set to "1," so a transmission interrupt request occurs when TIE is
set to "1." What does this mean? Does this mean that if the transmission interrupt is enabled when TDRE is "1," a
transmission interrupt request occurs?
Answer : Yes, that's right. The UART transmission interrupt occurs when no data is stored in SODR. For this reason, if the transmission
and transmission interrupt are enabled when no data is written to SODR, a transmission interrupt occurs.
When reception enable is resumed after UART reception has been disabled, FFH, which is not an expected value, is stored in
the first byte of reception data. Normal values (expected values) are stored in the second and subsequent bytes.
Answer : The cause is that UART reception is disabled and at the same time the counter operation stop (CNTE=0) of the 16-bit reload
timer is set under the condition that the baud rate clock source uses the 16-bit reload timer. Set the continuous operation
(CNTE=1) of the 16-bit reload timer.
When UART0 is used, the interval from the time when transmission data is written to the register to the time when the START
bit is transmitted varies within the 1-bit width of the transfer rate. Why? (Target: MB90F548G)
Answer:
UART0:The UART0 sampling clock is 1/8 the transfer rate clock but a transmission clock (T = 1-bit width of transfer rate)
for data transmission is available besides this sampling clock. Data is transmitted synchronously with this clock, so the
1-bit width deviation of the transfer rate occurs.
UART1:The UART1 sampling clock is 1/16 the transfer rate clock. Data is transmitted synchronously with this clock, so a 1/16-bit
width deviation occurs.
The chapter explaining UART0 in the manual mentions that reception operation is started after reset is released unless the
SIN0 input pin is fixed at "1." Why? (Target: MB90540G/545G series)
Answer : After reset has been released, the initial value of the UART0-related register is activated according to CLK synchronization
and transfer rate (clock obtained by dividing the internal operating frequency by 4: Baud rate generator). The reception enable
bit is unavailable and the SIN0 pin is "L," so the start bit is detected and a framing error occurs because the stop bit
is "L." When the SIN0 pin is kept at "L," repetition operation is repeated. In UART1, this symptom does not occur
because the prescalar stops and reception is disabled.
To perform 2 Mbps serial I/O communication, I want to install a capacitor as a radiation noise measure. Does current flowing
to the microcomputer influence serial I/O communication? Up to how larger capacitor can be installed?
Answer : Usually, 100 pF or 200 pF is used but that does not affect the microcomputer. 1,000 pF can also be used without any problem.
When the capacitor of more than 1,000 pF is used, you should calculate the current flowing to the microcomputer and examine
the assurance.
If a communication clock is given when transmission and reception are disabled and the SOT0 pin is in "L" status after
the UART transmission interrupt is completed, the SOT0 pin changes from "L" to "H" at the ninth clock. (Target: MB90650A
series)
Answer : When transmission and reception are disabled, a clock is transmitted also to the transmission shifter. When the clock is transmitted
for eight times, the transmission shifter is set to "FFH." This value is also transmitted to the latch of the last output
stage. When an external clock is transmitted later even once, the output pin changes to "H."
