Does watchdog stop for CPU sleep, time base timer, and stop mode?
Answer : Whether or not watchdog stops depends on types. For MB90560/ MB90565, MB904XX, and MB903XX (excluding 90390), since watchdog
does not stop for the sleep and time base timer, reset is used for return. In this case, in stop mode, watchdog stops because
the main oscillation stops.
Is the oscillation stabilization wait time generated after watchdog reset?
Answer : Generation of the oscillation stabilization wait time depends on a product. No oscillation stabilization wait time occurs
for MB903XX, MB904XX, and MB908XX. (MB90435 is excluded.) The stabilization wait time for which the WS1 and WS0 bits are set
is generated for MB905XX.
Explain roles of power-on reset and external reset (what kind of processing is performed internally?)
Answer : The power-on reset requires the oscillation stabilization wait time, but the external reset does not. In other functions,
both perform the same operations.
The hardware RST time is shorter than the oscillation stabilization wait time. At actual design, is there any problem if hardware
RST time is made longer than the oscillation stabilization wait time?
Answer : There is no problem even if the hardware RST is made longer than the oscillation stabilization wait time. In this case, the
CPU runs after the hardware RST time elapses. (A longer reset is validated.)
How long can the watchdog timer interval time be set?
Answer : The watchdog timer interval time varies depending on the FAIL/ SAFE policy in each system. The following advantages and disadvantages
depend on the time setting.
Shorter time setting: Fast detection of runaway (advantage) Software load is great. (disadvantage)
Longer time setting: Software load is small. (advantage) low detection of runaway (disadvantage)
WRST of the WDTC register is set. What status is that when power supply is suddenly turned off?
Answer : When power supply voltage is suddenly lowered, a WDTC register value is unpredictable (this, however, depends on the lowered
voltage). The value is currently set. This is because, as the cause of operation resulting from lowered power supply (operation
not guaranteed), it cannot be determined whether WDT is active or a register value is garbled. When the power supply monitoring
IC is used and power supply is lowered, the ERST bit of the WDTC register is set. So, this bit can be used to confirm that
power supply is lowered.
Teach me the differences in reset relating items between MB90495G series and MB90545G series. (Target: MB90495G/ 545Gseries)
Answer :
Difference in whether or not there are registers not initialized with reset input : See the attached data. For MB90540G and MB90545G, there are registers not initialized with reset input.
Difference in whether or not a direct transition is possible from PLL mode to sub mode : See the attached data. For MB90495G, a transition is possible from PLL mode to sub mode.
Difference in whether or not hardware standby is available : MB90540G series and MB90545G series have the HSTX function, while MB90495G series has no HST function.
The CPU does not run normally when the following procedure is performed: power supply voltage is lowered to about 0.5 V; the
CPU is started; then the external reset is canceled and the CPU does not run normally. However, the CPU runs normally when
a software reset is applied to the related routine. (Target: MB906XX, MB905XXseries)
Answer : Problems with registers not initialized with power-on reset (Possible problem is that some products have registers only initialized
with power-on reset). In this case, the reason why the CPU runs normally with software reset is as follows: LPMCR registers
are used to perform software reset and some of them are initialized only with power-on reset of CG1 and CG0; these registers
are also the LPMCR registers and so when software reset is applied, changes are made until CG1 and CG0 bits and the CPU runs
normally. To avoid this problem, be sure to initialize the uninitialized registers with the initialization routine.
