FAQ for F²MC-16LX Family

ICU/OCU

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1. Can I use one of the signals whose IC00 and IC01 inputs are ORed as a port? (Target:90520Aseries)
2. Can I use P20/IN00 as ICU input and P21/IN01 as a general-purpose port output? (Target:90520Aseries)
3. When the same value is input to output compare register 0 (OCP0) and output compare register 1 (OCP1), how is the output of these registers? (Level inversion is set when the value of compare register 0 matches that of compare register 1.)
4. The OUTD bit of the output comparison can be used to set the start level. Is the level at stop also set?
5. Values are set in the output compare output setting register (OTDx bit) but correct values are not output. What is the cause?

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Can I use one of the signals whose IC00 and IC01 inputs are ORed as a port? (Target: 90520A series)

• Answer :
  One of the signals cannot be used as a port. MB90520 input capture judges the signals ORed by being input from two pins. If one of the signals is used as a port, an edge occurs to affect capture operation.

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Can I use P20/IN00 as ICU input and P21/IN01 as a general-purpose port output? (Target: 90520A series)

• Answer :
  ICU mounted on MB90520A series inputs P20/IN00 and P21/IN01 to channel 0 via the internal OR circuit. When you use P21/IN01 as port output and P20/IN00 as ICU input, ICU operates as follows:
  
  • P21/IN01="LOW" output 　P20/IN00 → Detection of rising/falling edges OK
  • P21/IN01="HIGH" output 　P20/IN00 → Detection of rising/falling edges NG

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When the same value is input to output compare register 0 (OCP0) and output compare register 1 (OCP1), how is the output of these registers? (Level inversion is set when the value of compare register 0 matches that of compare register 1.)

• Answer :
  When the same value is input to output compare register 0 (OCP0) and output compare register 1 (OCP1), the output of these registers is the same as the output of one compare register.

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The OUTD bit of the output comparison can be used to set the start level. Is the level at stop also set?

• Answer :
  When the comparison operation stops, the level at stop is output.

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Values are set in the output compare output setting register (OTDx bit) but correct values are not output. What is the cause?

• Answer :
  The output compare setting register (OTDx bit) cannot be rewritten when compare operation is enabled. For this reason, the possible cause for incorrect value output is that values are written to OTDx bit when compare operation is enabled. We recommend to disable compare operation and to write values to OTDx bit in order to output values correctly.