FAQ for F²MC-16LX Family

I²C

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1. Even if master transmission (start condition generation instruction) is executed, a transfer end interrupt (INT bit=1) does not occur.
2. Is the stop condition interrupt supported?
3. After a start condition had occurred during master transmission execution, a communication error occurred because the slave (communication destination) drove the SDA line at a low level. Despite this fact, the master continuously outputs clocks. (Target: MB90F574A)
4. What happens if the I²C enters Stop Mode (SPL=0) during I²C transmission or reception? (Target: MB90370 series)

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Even if master transmission (start condition generation instruction) is executed, a transfer end interrupt (INT bit=1) does not occur.

• Answer :
  The I²C bus level may be SCL=L and SDA=L. If the start condition generation instruction is executed in this status, a transfer end interrupt (INT bit=1) does not occur because the master cannot output a clock. Once this status occurs, the BB bit is set to "0" and the AL bit is set to "1." Detect this status with the BB and AL bits to disable I²C and release the status.

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Is the stop condition interrupt supported?

• Answer :
  The stop condition interrupt is not supported. It is necessary to monitor the BB bit with software to detect the stop condition.

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After a start condition had occurred during master transmission execution, a communication error occurred because the slave (communication destination) drove the SDA line at a low level. Despite this fact, the master continuously outputs clocks. (Target: MB90F574A)

• Answer :
  After a master condition has occurred during master transmission execution, I²C mounted on an FMC family always outputs nine clocks when SCL is free.
  After nine clocks have been output, an INT bit interrupt flag occurs to cause the interrupt. It is necessary to confirm each flag in this interrupt routine.
  Immediately after a bus error has occurred, a bus error interrupt occurs and I²C is automatically disabled with hardware.

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What happens if the I²C enters Stop Mode (SPL=0) during I²C transmission or reception? (Target: MB90370 series)

• Answer :
  
  • In Master mode (clocks are output)
    I²C enters stop mode during I²C transmission or reception. After the stop mode has been released, I²C outputs remaining clocks.
    In the stop mode, the SCL and SDA pins retain the status immediately before transition to the stop mode (SPL=0).
  • In Slave mode (clocks are not output)
    I²C enters stop mode during I²C transmission or reception. After the stop mode has been released, I²C waits for the input of remaining clocks.
    In the stop mode, the SCL and SDA pins retain the status immediately before the transition to the stop mode (SPL=0).