Teach me the priority order used when interrupts of the same level occur at the same time
Answer : The chapter on interrupts in the manual provides interrupt vector numbers. When interrupts of the same level occur at the
same time, an interrupt with a smaller interrupt vector number is given processing priority.
How long does it take from input of an external interrupt until execution of interrupt processing?
Answer : An interrupt of this CPU is accepted in the final cycle of each instruction. So, interrupt acceptance depends on the instruction
being executed. After the interrupt is accepted, interrupt processing is performed after the interrupt handling time elapses. For details, see the hardware manual of each product.
When an interrupt request occurs during interrupt processing, can the request be retained?
Answer : When the level of interrupt generated during interrupt processing is higher than the level of interrupt being executed, the
interrupt routine migrates. When the level of the generated interrupt is lower a transition is made to the interrupt routing
after the routine being executed ends.
When an interrupt request having the same priority level as the interrupt being processed is generated during a certain type
of interrupt processing, does a multiple interrupt occur?
Answer : No multiple interrupt occurs. An interrupt request newly generated is retained. It is accepted after the interrupt being processed
ends (interrupt processing is executed)
If a higher interrupt request occurs immediately after an interrupt request, when is the higher request started?
Answer : If both interrupts occur at the same time, the higher interrupt is processed. However, once a lower interrupt enters into
the handling time, no other interrupts are accepted during that processing. Therefore, the higher interrupt handing starts after the handling time of the executing interrupt ends.
Does an interrupt occur if a pulse equal to or less than the input standards of an external interrupt is input?
Answer : The input standard of an external interrupt is specified with the width of pulse, and normal execution of interrupt processing
is guaranteed when a pulse having a width greater than the standard value is input. Interrupt processing may occur even if a pulse equal to or thinner than the external interrupt input standard width is entered. However, this operation is not guaranteed. So, we recommend to use a pulse meeting the standard.
External interrupt processing is unstable after reset is cancelled
Answer : EIRR of the interrupt factor register need be initialized because the initial value is undefined. An unintended interrupt may occur unless the following items are set in this order during program process: 1. ELVR (interrupt),
2. EIRR (factor) clear, 3. ENIR (interrupt enabled)
Change of an ILM interrupt level within an interrupt routine.
Answer : Changing ILM levels within the interrupt routine is generally used to avoid interrupts that are generated by changing ILM
levels to higher levels .Take care that, when an ILM level is changed to a lower level within the interrupt routine, an interrupt
being executed may recur for multiple interrupts.
A level and edge can be selected when an external interrupt is used. However, teach me the sampling method of interrupt detection
(Target: MB90495G)
Answer : The sampling clock is an internal operation clock. (1) For level detection, a level is determined by one sampling, (2) For
edge detection, an edge is determined as compared with the last value.
The item on the interrupt processing time in the hardware manual describes the wait time for transiting to interrupt processing.
However, is there no specification of the wait time for returning to the original status after the interrupt processing ends.
Answer : For the interrupt return time, there is only the RETI instruction execution time. For the interrupt transition, the time for
handling the interrupt is required to transit to an interrupt processing during processing of a CPU instruction. However,
for return, no special time is required because instructions are processed sequentially.
The item on the interrupt sampling time in the chapter on interrupts in the manual describes that "the interrupt request
sampling wait time is the maximum when an interrupt request occurs immediately after the start of POPW RW0,...RW7 instructions
(45 machine cycles) having the longest execution cycle." Teach me the expression for calculating the 45 machine cycles.
Answer : The instruction list indicates that the number of POPW rlst cycles is 7 + 3 × (number of times of POP) + 2 × (last register
number for POP). Therefore, the number of cycles for which POPW occurs from RW0 to RW7 is 7 + 3 × 8 + 2 × 7 = 45 cycles.
Can I perform clear processing of the watchdog timer by using a fixed cycle interrupt such as a timer?
Answer : We do not recommend this method because, when the fixed cycle interrupt such as a timer is used to perform the clear processing
of the watchdog timer, the effect of the watchdog timer is reduced by half.
Is the watchdog timer running in stop mode of a microcomputer?
Answer : In microcomputer stop mode, the watchdog stops because oscillation stops. After a return from the stop mode, the watchdog
counter is cleared and the watchdog operates.
Answer : We recommend to collectively set the unused interrupts in the same vector as the reset vector or to set a fixed processing
routine to handle them.
What happens when an undefined instruction is executed?
Answer : In FMC-16LX series, an exception interrupt is generated by executing the undefined instruction. By defining reset vector to the exceptional interrupt, the processing returning from the exceptional interrupt and reset can
be executed.
How is a PC value to be saved to the system stack at exceptional interrupt occurrence?
Answer : The exceptional interrupt occurs when an undefined instruction is executed. The program address containing the undefined instruction
is saved to the system stack. Note that the stack operation of the PC value is different for an ordinary interrupt.
