How long does it take to return from sleep mode and stop mode with an external interrupt?
Answer : Return from sleep mode with an external interrupt requires interrupt handling time (maximum of 48 cycles). Transition to PLL
mode via software requires PLL stabilization wait time. Also return from stop mode requires main clock oscillation stabilization
wait time.
I want to know sub clock stabilization wait time. (Target: MB905xx series)
Answer : Sub clock stabilization wait time is fixed at the 2^14 cycles. This sub clock stabilization status can be detected with the
SCE bit of the clock timer control register. When "0," the SCE bit indicates sub clock stabilization wait time.
The manual mentions that after 1 (main) has been written to MCS, 0 (PLL) may be unable to be written during a maximum of 8
machine cycles. Is this true? (Target: MB905XX series)
Answer : A maximum of machine clocks of writing enable period depends on a PLL multiplication number. For example, 4 multiplication
and main clock (dividing the clock by 2) are applied, so a maximum of eight clocks is required (maximum time at which the
PLL clock detects a main clock edge). Basically, we recommend to confirm main clock with MCM and then switch to PLL. In this
specification, the MB904XX series core is not restricted to use (however, care must be taken for MB90435 series where a core
of MB906xx is used).
The manual mentions that CS1/CS0 multiplication should be set when MCS is "1" status. What happens if I set CS1/CS0 multiplication
and MCS at the same time?
Answer : Basically, we recommend that you set MCS to "1" and then set CS1/CS0 as the manual mentions. However, if you set MCS to
"0" and at the same time of changing CS1/CS0, CS1/CS0 change is valid.
When sub clock mode switches to PLL mode or main clock mode switches to sub clock mode, the CPU sometimes operates in sub
clock mode without switching to main clock mode.
Answer : Have you ever set SCS to "0" and then SCS to "1" again before SCM is set from "1" to "0"? When you switch
SCS frequently, make sure that CPU status transition is perfectly completed with SCM and then write SCS.
If an external reset is input when the CPU is operating on a sub clock, is there any possibility that the CPU performs reset
operation without waiting for the oscillation stabilization wait time?
Answer : If an external reset is input when the CPU is operating on a sub clock (status in which the main clock is stopped), the CPU
performs reset operation after the oscillation stabilization wait time has elapsed. (That is, the CPU uses the same sequence
executed if a reset is input when the CPU is operating in stop mode in which the main clock is stopped.)
I want to know the time required to switch PLL one time to PLL quadruple and the time required to switch PLL quadruple to
PLL one time in PLL internal machine clock switching.
Answer : You cannot switch a multiplication number during PLL operation. To switch a PLL multiplication number, be sure to switch PLL
mode to main clock mode once, set the PLL multiplication number again, and then switch main clock mode to PLL clock mode.
In this case, the time required to switch to main clock mode is about 8 clocks. The time required to switch to PLL clock mode
is 213 clocks. For details, see the clock specification to be separately issued.
If an interrupt occurs during multiplication switching, how does the CPU operate?
Answer : The CPU operates on the PLL clock or main clock during multiplication switching. For this reason, we think that the overlap
of CPU operation with switching timing does not arise as a CPU instruction problem. (In resources, the clock changes as shown
above.)
I'm using external clock 8 MHz with 2 multiplication (internal 16 MHz). Can I switch this to external clock 8 MHz with 1 multiplication
(internal 8 MHz)?
Answer : To change a multiplication rate, change the clock to the main clock once (MCS=1), change the multiplication rate (CS1, CS0),
and then start PLL (MCS=0).
Is there any negative effect that can be used when a clock is switched during operation? I also want to know the details and
influence of resources that use an external clock and resources that use a post-multiplication machine clock.
Answer : Basically, resources other than the time base timer use post-multiplication clocks as a clock source. For this reason, the
resource timing also changes in proportion to multiplication clock change.
If voltage is recovered after the power supply has decreased from 1.2 V to 0.8 V due to power glitch, is there any possibility
that the CPU malfunctions?
Answer : If the power supply is turned on after it has decreased to a halfway voltage (1.0 V or lower), the register that was not initialized
despite power-on reset by the CG1 and CG0 bits of the LPMCR register may be started. For this reason, normal operation may be unable to be confirmed if the register starts operating at the slower clock cycle
that the software does not intend. In this case, initialize the register with the initial routine or use HSTX instead of external reset.
Notes on EI2OS are written as follows: If a resource allocated to the same ICR uses EI2OS, it cannot use the remaining interrupts.
Why?
Answer : EI2OS is started with an interrupt factor, so if the resource uses EI2OS, the EI2OS count may be incremented also in remaining
interrupt factors. For this reason, the resource usage is restricted.
If EI2OS operation by an interrupt is enabled, when is the interrupt routine executed?
Answer : If EI2OS operation is enabled, the interrupt routine is not executed till data of the data counter value set in the descriptor
is automatically transmitted.
When I want to transmit data repeatedly with EI2OS after data of the data counter value set in the descriptor has automatically
been transmitted, what should I do?
Answer : After data of the set data counter value has been automatically transmitted, reset the descriptor in the interrupt routine
and start EI2OS.
Is it possible to transfer data with uDMA and EI2OS although sleep mode has not returned to normal mode? At this time, the
interrupt level that occurred is assumed to be IL=7.
Answer : When an interrupt of IL=7 occurs in sleep mode, sleep mode does not return to normal mode. Also uDMA and EI2OS do not operate.
Teach me the data reading method of dedicated register PS or CCR.
Answer : It is necessary to stack data on memory with the PUSHW PS instruction and to read the stacked data. However, the dedicated register cannot read data on a C source.
Answer : The 4-byte instruction queue is a buffer that stores the next instruction to be pre-read. The instruction queue enables instruction
fetch during instruction execution, so the instruction fetch cycle can be shortened.
I think that when a CPU runaway occurs, the PC jumps to a free ROM area and performs some kind of operation there. What processing
should the PC do from the view point of a CPU?
Answer : We think that it is desirable to pad the free ROM area with undefined instructions. We also think it is desirable that FMC-16LX
series dare to pad the free ROM area with undefined instructions to cause an exceptional interrupt and perform necessary processing
(e.g., LOG write to E2PROM) for reset. This is because when an undefined instruction is executed, an exceptional interrupt
occurs.
The hardware manual mentions that the capacitance of the capacitor for power smoothing to be connected to VCC should be greater
than the capacitance of the ceramic capacitor to be connected to the C pin. The hardware manual also recommends that the
capacity of the ceramic capacitor to be connected to the C pin be 0.1uF. Does this mean that the capacitance of the capacitor
to be connected to the VCC pin should be 0.1uF or greater? If the capacitance of the ceramic capacitor to be connected to
the C pin is greater than the capacitance of the capacitor to be connected to VCC, do errors such as malfunction occur?
Answer : Some products have a built-in voltage step down circuit. We recommend that the C pin of a microcomputer be equipped with 0.1
uF to absorb the output voltage power fluctuations of the voltage step down circuit. The Vcc pin serves as input to the voltage
step down circuit but a noise that occurs in voltage step down circuit output may also occur in the Vcc pin. For this reason,
we recommend that the capacitance of the capacitor to be connected to the Vcc pin be greater than the capacitance of the capacitor
to be connected to the C pin.
The data sheet mentions that the PLL 2 bit is set when 20 MHz to 25 MHz of the PLL clock are used. What does this mean? (Target:
MB90480 series)
Answer : Taking internal operating frequency of 24 MHz as an example, this means that you should set 12 MHz with 1 multiplication and
the PLL 2 bit to "1" (twice). That is, this means that 24 MHz oscillator with 1 multiplication cannot be set.
The manual mentions that it takes a maximum of 80 us to return to the external interrupt from the pseudo watch. Does this
depend on an internal clock? (Target: MB90435 series)
Answer : This circuit uses a maximum of 80 us as the internal voltage step down circuit stabilization time. This does not depend on
clocks such as an internal clock and means that this is analog time management.
When I set two addresses with the address coincidence function, is there any method for judging which address is used?
Answer : As the manual mentions, the address coincidence function has only the AD1E and AD0E operation enable/disable flags. For this
reason, you should judge which address is used with SP PC.
At reading the data register to clear the UART reception interrupt flag before standby processing, a delay interrupt occurs
sometimes. What is the cause? (Target: MB90435 series)
Answer : A possible cause is that UART reception interrupt flag clear processing exists in the main routine and the UART reception
interrupt is enabled. When these settings are implemented at the same time, an internal conflict that causes an interrupt
source to be cleared according to the timing of interrupt processing occurs in the CPU. In this case, the CPU switches to
a delay interrupt with the largest interrupt number. To avoid this symptom, take countermeasures such as disabling the UART
reception interrupt before clearing the UART reception interrupt flag.
As a result of the noise test, a symptom appears which seemingly indicates the operation stop of the microcomputer itself.
Is there any method for checking the operation of the internal voltage step down circuit? (Target: MB90F387)
Answer : Confirm the voltage of the external C pin. You can usually detect about 3 V when the voltage step down circuit is operating
normally.
