Features

The FR Family of products consists of new-generation microcontrollers featuring the superb processing capacity of RISC and the embedding functions of 16-bit technology.
To respond to future specification requirements, the architecture of the FR Family was designed specifically for embedded applications based on the following goals: (1) Advanced processing capacity; (2) Addition of commands necessary for embedded applications onto a RISC command base; (3) High object efficiency; and (4) Abundant peripheral functions.

Internal block diagram

(1) Advanced processing capacity

The CPU has a high processing capacity of 1.25 commands per clock (Dhrystone benchmark core functions). When operating at 50 MHz, core performance reaches 64 VAX MIPS.

To efficiently drive the 5-stage pipeline, the internal buses incorporate the Harvard bus architecture, similar to such high-performance RISC processors as SPARC.

These features, combined with such functions as a multiplier, a program counter adder, and barrel shifter, enable the FR Family of products to provide the same superior degree of performance as conventional RISC processors.

(2) Additional commands necessary for embedded applications

Based on what is called load/store architecture, standard RISC undertakes external access via load and store alone.

Additionally, embedded microcontrollers require a number of frequently used commands to be combined. For the development of the FR Family, Fujitsu surveyed a wide range of memory-access methods and commands that were frequently used in embedded applications,

then added such commands as memory-to-memory transfer, peripheral resource control, bit management, immediate data command, and barrel shift. Furthermore, in anticipation of the growing size of system applications, the need for shorter development periods, and increased use of the high-level C Language in development applications, Fujitsu provided commands to perform stack frame generation/release and simultaneous loading and storing of multiple registers into the stack at function call entry and exit. Although one of the features of RISC is that some of these commands cannot be incorporated into its hardware-wiring commands, Fujitsu nevertheless considers them essential for embedded applications. As a result, the FR Family supports 160 such commands, rivaling the performance of an 8-bit microcontroller.

(3) High object efficiency

Through the use of compact 16-bit fixed-length commands and a group of 160 commands that are suitable for embedded applications, the FR Family has achieved the same level of object efficiency as a 16-bit microcontroller.

High object efficiency means a reduced number of external-memory access operations and less

cache usage, resulting in a lower external bus load, improved cache efficiency, and more efficient operation of the high-performance CPU core.

(4) Abundant peripheral resources

The FR Family incorporates buses that are electrically equivalent to those of Fujitsu's 16-bit F²MC-16 Family of microcontrollers (R-BUS in the block diagram). When connected to these buses, the FR Family can use resources widely available to the F²MC-16 Family (with the exception of resources that require direct FR bus connection and high-speed operation, such as DMA and DSP resources).
Furthermore, incorporating FR Family into ASIC as a CPU core (as currently planned), can be achieved from the various macros according to their uses.

Macro examples: A/D, D/A, UART, serial, timer/counter, I²C, CAN, PWM, and so on