F²MC-16LX Family Features

F²MC-16LX family is a high-performance 16-bit microcomputer having the upward compatibility with the F²MC-16L family.

Registers
Dedicated registers
General-purpose registers: 10 x 16-bit per bank, 32 banks Max.

Clock multiplier circuit (x1/2, x2, x3, and x4) to protect your surrounding environment
Reducing the radiation interference
High-speed operation using the inexpensive low-speed oscillator (external 4 MHz; internal 16 MHz max.)
Power management capabilities to contribute to the conservation of energy:
STOP, SLEEP, subclock, hardware standby
AL 2 layers 0.5 µm (reducing the chip footprint)
Low-voltage, low-power voltage dissipation
Supporting large memory (up to 256 Kbytes for ROM; up to 10 Kbytes for RAM)
Power dissipation reduced by 60 % as compared to the earlier product (5V compatible product)

Noise protection
Adoption of multiplier circuit
Circuit optimization
Built-in noise filters for all pins
Bus control
Bus sizing function: 8-bit or 16-bit bus width selectable
Software switching between non-multibus and multibus (device)
Supporting 8 ch. chip select (device)
Built-in extended intelligent I/O service function (simple DMA function)
Program patch processing function
Avoiding bugs by applying patches on a masked ROM
Addition of signed multiplication and division instruction
High-speed interrupt transition
High-speed transition achieved at the time of multiple interrupts

Expansion achieved to low-voltage and high-speed operation
5.0 V: Minimum machine clock of 62.5 ns/16 MHz
2.2 V: Minimum machine clock of 100 ns/10 MHz

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