F²MC-8L Family Features

• Minimum execution time: 0.32ms/12.5MHz, 0.4 ms/10MHz, 0.95 ms/4.2 MHz
• Operating voltage: +2.2 V to +6.0 V, operating frequency: 1 MHz to 10 MHz
• Software-switchable instruction cycle (4 speeds) provides low voltage, low-power consumption operation (clockgear function)
• Backup voltage in stop mode (voltage required to maintain RAM data): Min. +1.5 V
• Bitwise selectable pull-up resistors for each I/O port
• One-time PROM products support (by programming data) the same option settings as mask ROM products (the option settings are mask options for some products).

• Memory space: Max. 64 Kbytes

• Memory mapped I/O
• Registers
  Dedicated registers
  General-purpose registers: 8 x 8-bit per bank, Max. 32 banks

• Enhanced interrupt function (prioritized multiple interrupts)
• Powerful operation and transfer functions
  Multiplication and division instructions: 8-bit x 8-bit = 16-bit (7.6μs/10MHz), 16-bit / 8-bit = 8-bit (8.4μs/10MHz)
  Data transfer: Max. 16-bit
• Number of instructions: 136

F²MC-8FX Family Features

• Minimum execution time: 100 ns/10 MHz
• Operating voltage: +1.8 V to +3.6 V or +3.0 V to +5.5 V, external clock: 32.768 kHz to 20 MHz
• Software-switchable instruction cycle provides low voltage, low-power comsumption operation (clock gear function)
• Backup voltage in stop mode (voltage required to maintain RAM data): Min. +1.5 V
• Bitwise selectable pull-up resistors for each I/O port
• Memory space: Max. 64 Kbytes

• Memory mapped I/O
• Registers
  Dedicated registers
  General-purpose registers: 8 x 8-bit per bank, Max. 32 banks

• Enhanced interrupt function (prioritized multiple interrupts)
• Powerful operation and transfer functions
  Multiplication and division instructions: 8-bit x 8-bit = 16-bit (0.8μs/10MHz), 16-bit /16-bit = 16-bit (1.7μs/10MHz)
  Data transfer: Max. 16-bit
• Number of instructions: 136

F²MC-16L Family Features

• Faster version of the F²MC-16 (MB90700 series) with object code compatibility and also allows low voltage operation.
• Easy programming with plenty of data types, including bit (1-bit), nibble (4-bit), byte (8-bit), word (16-bit), and long word (32-bit), and 23 types of addressing.

• Bank and linear support of 16Mbytes memory space makes easy migration from external memory sizes to singlechip systems.

• Registers
  Dedicated registers
  General-purpose registers: 10 x 16-bit per bank, 32 banks Max.

• Pipeline processing using 4 bytes cue (minimum instruction execution time: 62.5 ns/16 MHz)
• Powerful real time processing using 8-level hardware support priority interrupts and extended intelligent I/O service functions.
• Extended C language and real time operating system instructions (SP indirect addressing, etc.)
• Can utilize external 4 MHz oscillator to run at 16 MHz internally by using a built-in clock multiplier circuitry.
• Number of basic instructions: 340 (fully compatible with the F²MC-16/16H)

F²MC-16LX Family Features

• F²MC-16LX family is a high-performance 16-bit microcomputer having the upward compatibility with the F²MC-16L family.

• Supporting 16-Mbyte memory space.

• Registers
  Dedicated registers
  General-purpose registers: 10 x 16-bit per bank, 32 banks Max.

• Clock multiplier circuit (x1/2, x2, x3, and x4) to protect your surrounding environment
  Reducing the radiation interference
  High-speed operation using the inexpensive low-speed oscillator (external 4 MHz; internal 16 MHz max.)
• Power management capabilities to contribute to the conservation of energy:
  STOP, SLEEP, subclock, hardware standby
• AL 2 layers 0.5 µm (reducing the chip footprint)
• Low-voltage, low-power voltage dissipation
  Supporting large memory (up to 256 Kbytes for ROM; up to 10 Kbytes for RAM)
• Power dissipation reduced by 60 % as compared to the earlier product (5V compatible product)

• Reduced power dissipation (5V compatible products)

• Noise protection
  Adoption of multiplier circuit
  Circuit optimization
  Built-in noise filters for all pins
• Bus control
  Bus sizing function: 8-bit or 16-bit bus width selectable
  Software switching between non-multibus and multibus (device)
  Supporting 8 ch. chip select (device)
• Built-in extended intelligent I/O service function (simple DMA function)
• Program patch processing function
  Avoiding bugs by applying patches on a masked ROM
• Addition of signed multiplication and division instruction
• High-speed interrupt transition
  High-speed transition achieved at the time of multiple interrupts

• Expansion achieved to low-voltage and high-speed operation
  5.0 V: Minimum machine clock of 62.5 ns/16 MHz
  2.2 V: Minimum machine clock of 100 ns/10 MHz