FAQ for network designing | FAQ about parameter designing |
Flex Ray FAQ
FAQ for network designing
- Network vector
- Sending end bit
- CC disconnection detection
- Receiving buffer and received data
- DTS inconsistency check
- How to handle Sync Frame Overflow
1. Network vector
Question 1
When the last of the cycle of the network vector is reset to "0." At that time, if the host has locked this register,
how does the system work?
Answer
The status register of the network vector is not locked by the host.
There are two types of operations (double buffer), one is for a register for updating, and the other is a register for host
display. The register for updating is reset to 0 at the end of a cycle, and in the next cycle, when the network vector is
received, the register for updating is written with OR condition. At the end of the next cycle, the contents of the register
for updating is copied to the register for host display.
Accordingly, the register for host display contains the network vector information of the last cycle. Complete the processing
(such as read processing) within a cycle, if necessary.
Question 2
The network vector is supposed to be written with OR condition as usage, what usage is assumed for this specification?
Answer
A bit position of this network vector is assigned to each node separately. Each node sends a static frame with the status
information (such as error) to the assigned bit position.
The receiving node applies the OR condition to the received network vector information so that the statuses of all nodes can
be identified.
If the network vector information of a cycle is not enough, divide the contents into each cycle to obtain all necessary information.
2. Sending end bit
Question 1
The CC sets the sending end bit to notify the host of the end of sending. What are the conditions for the notification?
Answer
The sending end bit is set when the MBI flag (message buffer interrupt enable) that is controlled by each message is enabled
and when the sending ends.
The sending end event occurs when the sending enable TxEN between CC and BD is changed to disable ("0" to "1") from
enable.
The MBI flag can be set for each message when the header session information is written.
3. CC disconnection detection
Question 1
Can CC detect if the sending failed due to the disconnection of TxD between CC and BD? Can CC also detect the short-circuit
of the bus?
Answer
When TxD is disconnected, if "L" level is output to the bus, the receiving node detects the syntax error (protocol error).
If "H" level is output to the bus, it is the same as IDLE state, so the receiving node cannot detect the error. In such
cases, a node is allocated to a cycle to send MTS to the symbol window to check whether the receiving node can receive it
unless the BG is mounted. Alternatively, duplicate the bus (redundant configuration,9 and compare the data of Ach and Bch.
If the short-circuit of the bus (disconnection) occurs, the receiving node detects the syntax error (protocol error).
These error detections are monitored by using the network management to check which node is failed and to control the network.
4. Receiving buffer and received data
Question 1
When a slot receives several frames, which data is stored in the receiving buffer?
Answer
The valid frames and invalid frames may coexist.
- Received data ( PDF 16KB）
5. DTS inconsistency check
Question 1
Is the inconsistency (existence or exceeding the minimum value) of DTS checked?
Answer
The inconsistency (existence or exceeding the minimum value) of DTS is checked.
6. How to handle Sync Frame Overflow
Question 1
When the Sync Frame Overflow occurs, the host can obtain the information, but the communication continues. What kind of usage
is assumed for this handling?
Answer
The Sync Frame Overflow event of the synchronized frame is not considered as a serious error because of the following reasons, so the communication continues.
[Reason]
Basically, FlexRay must operates using the pre-determined number of synchronized nodes or fewer. However, if the synchronized
frames more than synchronized nodes are received, the synchronization processing will performed according to the fault tolerant
midpoint algorithm (FTA/FTM). If an abnormal synchronized frame is input, it is excluded by FTA/FTM. Therefore, the error
is not considered as a serious synchronization error.
The following usages are assumed.
The maximum number of synchronized nodes can be specified in the parameter for a register at network settings. If an invalid
value (a value smaller than the number of synchronized nodes) is specified for the maximum number, Sync Frame Overflow is
detected. In such cases, change the setting to an appropriate value of the maximum number of the synchronized nodes.
Also, after the network setting (after system in), if an unexpected (such as post-attached) synchronized node is integrated
(joined), it can be detected. In such cases, the clock synchronization is maintained according to the synchronization algorithm
with the specified maximum number of synchronized nodes.
This event is used for detecting an error of the network settings, and it can lead to appropriate correction of parameters.
Also, an incorrect synchronized frame due to a bus error is not supposed to be received because it is prevented by the header
CRC.
