For the most-advanced technologies from 28 nm to 0.18 µm, information on the ASIC products best suited for the customer's products are provided.

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The Standard cells, by optimizing chip sizes, realize LSIs with higher integration and performance than macro-embedded cell arrays.
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On the gate arrays, macros whose sizes are optimized at the transistor level can be implemented, realizing high-performance LSIs. A wide range of frames can be offered to the customers.
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Chips where transistors (basic cells) are regularly placed are prepared. In them, only routing is provided. Thus, Gate arrays feature shorter development time.