SPARC64™ V with its 90nm architecture, means faster clock speeds, high integration, and low power consumption. SPARC64™ V maximizes server system potential by eliminating a range of internal processor performance-related bottlenecks that reduce the performance of other processors, providing more balanced memory access and computing power.

These and other design considerations allow SPARC64™ V to exhibit a high throughput in a wide range of processing environments, from general applications to large-scale online transaction processing .

High Performance Features

The use of multiple instruction execution units, makes it possible to execute multiple instructions in parallel, independently. With SPARC64™ V, it is possible to decode four instructions and input them into six arithmetic/logic units at the same time.

Regardless of the order in which instructions are written in a program, instructions are executed once all the necessary data is ready to be processed. This reduces processing wait times as subsequent data ready instructions will be processed while the system waits for the data necessary to process the preceding instruction.

The incorporated branch prediction function predicts which instruction sequence a program will follow to reduce wait times during branch processing.

Data needed for a specific instruction processing if not cached can be fetched from memory and passed through cache without interfering with other processing functions.

Based on the regularity with which a program accesses cache, subsequent data accesses are predicted by the hardware itself, with all necessary data transferred from the main memory to cache in advance.

The number of instructions that can be issued successively from the processor to memory or disk without awaiting a response is referred to as the "outstanding number." SPARC64™ V offers a higher increased outstanding number than the SPARC64™ GP.