Fujitsu Achieves World's Fastest Transceivers of 32 Gbps for Inter-Processor Data Communications

Kawasaki, Japan and Sunnyvale, CA, February 18, 2013

Fujitsu Laboratories Limited and Fujitsu Laboratories of America, Inc. today announced the development of transmitter circuits, equalizer circuits for transmission loss, and receiver circuits capable of communicating at 32 Gbps, the world's fastest speed to date. These developments will support inter-processor communications in the next-generation of servers.

Along with increases in CPU performance in recent years, the data processing capabilities of servers have improved greatly, leading to a need for faster data communications between chips and between circuit boards. Through the development of a new kind of transceiver circuit, along with an equalizer circuit that can compensate for signal degradation in transmission lines, Fujitsu Laboratories has made it possible to roughly double data communications speed between CPUs.

These new technologies are expected to lead to improved performance in the next-generation of servers and supercomputers.

Details of the new technologies will be presented at the IEEE International Solid-State Circuits Conference 2013 (ISSCC 2013), beginning Sunday, February 17, 2013 in San Francisco (ISSCC presentations 2.7, 2.1, and 2.5).

Background

In recent years, there has been a greater need for improvements in data processing performance for servers employed in datacenters, which support cloud computing and other applications. This has led to enhancements in CPU performance, as well as the development of large-scale systems that connect large numbers of CPUs. As a result, the amount of data traffic exchanged between CPUs and peripheral devices has grown substantially. To accommodate this high volume of traffic, inter-processor data communications speeds in today's servers have increased from a few Gbps to tens of Gbps. In anticipation for the next generation of high-performance servers, expectations are growing for communication speeds to increase even further.

Technological Challenges

Increasing the speed of inter-processor data communications requires that both transmitter circuits and receiver circuits operate at higher speeds. Moreover, signal degradation over transmission lines, such as electrical wiring on printed circuit boards, becomes more significant at higher speeds. Therefore, when operating at higher speeds, equalizer circuits necessary to compensate for this transmission loss also require performance improvements.

Newly Developed Technology

The inter-processor data communication unit is broadly divided into a transmitter unit and a receiver unit. The latter consists of 1) an equalizer circuit that compensates for signal degradation over transmission lines and 2) a receiver circuit that reads the original data from the restored signals (Figure 1). By employing new kinds of technologies in the transmitter circuits as well as in the equalizer and receiver circuits within the receiver unit, Fujitsu Laboratories has succeeded in improving communication speeds.

1. Transmitter circuit (ISSCC presentation 2.7)

Transmitter circuits transmit data from multiple channels that have been multiplexed into a single channel. The final-stage multiplexer not only consumes considerable amount of power, but also will approach the limit of its operating speed as data rates increase. Fujitsu Laboratories has developed a transmitter circuit that eliminates the need for a final-stage multiplex circuit (2-to-1 multiplexer). Rather than using conventional binary values (0, 1) in the transmitted signals, the new circuit uses ternary values (0, 1, 2). This makes it possible to restore the original data on the receiving end using only the existing receiver circuit functionality, without having to add any special circuitry (Figure 2, left). As a result, it exceeds the speed limit of conventional transmitter units. This is also why power consumption can be reduced by roughly 30% compared to the existing technology (Figure 2, right).

2. Equalizer circuit in the receiver unit for transmission loss (ISSCC presentation 2.1)

The quality of the signal output from the transmitter unit degrades as it is carried across printed circuit boards and other transmission lines. The scale of degradation is greatly magnified depending on the length of the transmission lines and the speed at which the signal travels. Accordingly, signal loss increases as speeds accelerate, even over the same transmission line. Conventionally, applying loss-compensation to the signal attenuation produced at high frequencies results in flat frequency response, thereby compensating for distortion. But as the signal band for high-speed transmission extends even farther into the high frequency range, the drop-off in low-end frequency response, which previously was not a problem, makes it impossible to adequately correct the distortion. Fujitsu Laboratories has developed a circuit that compensates for signal loss by flattening the frequency response at low frequencies. This technology has made it possible to carry a signal at 32 Gbps over a transmission distance of 80 cm, which was previously not possible (Figure 3).

3. Receiver circuit in the receiver unit (ISSCC presentation 2.5)

The receiver circuit reads the original data from the signal that has been reshaped by the equalizer circuit for transmission loss. When this occurs, it is necessary to synchronize the speed (frequency) and timing (phase) of the signal, perform sampling on the signal, and determine the original digital values. Conventionally timing errors, which occur when reading data, would be detected from the source data by a timing error detection unit, and they would then be processed through resynchronization via a timing modulation circuit (Figure 4, upper left). But at higher signal speeds, this method requires the time precision that controls the clock to reach a level of precision at the limit of existing technologies. Instead of synchronizing the clock, Fujitsu Laboratories has developed a data interpolation method in which data is periodically sampled and voltage interpolation processing is applied, based on two actually sampled signals, to synthesize a virtual signal that is synchronized to the clock (Figure 4, lower left & right). This technology obviates the need for a timing modulation circuit requiring high resolution in the time axis, making it amenable to further speed increases in the future.

Results

These technologies are expected to significantly contribute to performance improvements in the next-generation of servers and supercomputers.

Future Development

Fujitsu Laboratories will work to apply these technologies to product areas related to big data, such as the backplane interfaces that link the boards together in the servers.