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Fujitsu PLL architecture
Pictured is the block diagram depicting the architecture of a typical Fujitsu Super PLL, the MB15E07L.
As can be seen, all of the features of the simplified block diagram are present. All parts in the same series have an identical architecture, and all super PLLs in the current Fujitsu product offering have similar architectures with minor differences.
Reference oscillator
All super PLL devices have an input port to provide the PLL with a reference signal. In the example below there is an internal oscillation circuit which can be configured as an input buffer amplifier as shown in figure 3, or as a crystal oscillator as shown in figure 4.
In the diagram in figure 3, the reference source is shown AC coupled to the input pin OSCin, while the output pin OSCout is left open. Direct coupling is also possible but requires that the reference source exceeds the threshold of the input buffer. As the average DC bias level of the reference source will be different from the threshold level, the duty cycle of the reference signal at the output of the internal buffer will not be 50/50. This will affect the synthesiser performance. In the diagram in figure 4, the internal oscillation buffer generates the reference signal for the PLL with the external capacitors and crystal defining the output frequency. Care should be taken to minimise the size of the capacitors to ground including the strays caused by the PCB, and the load due to the input capacitance of the crystal. It is not recommended that the total load on each pin exceed 20pF. The values of C1 and C2 are generally recommended by the crystal manufacturer.
Several devices (All 'F' series, All 'S' series) feature only a reference input pin due to package size limits, therefore only the configuration shown in figure 3 is possible, a typical representation of the reference input frequency range and sensitivity, when used in this manner is pictured in figure 5 below.
An example of the input impedance of the input buffer is pictured in figure 6.
Reference divider
The reference input is divided by a counter, (hereafter referred to as the R counter) before application to the phase detector for comparison with the divided VCO signal.
VCO input buffer
The VCO input is applied to the IC through a high frequency differential buffer as shown in figure 7. The output level of the VCO can be attenuated to the minimum level required to stimulate the input buffer. It is always preferable to operate close to the minimum level as it helps minimise crosstalk in particular to the tuning point of the VCO, which could cause unnecessary spurii on the generated high frequency output signal. The capacitor to ground can be omitted with a loss of input sensitivity. AC coupling is required as the input buffer generates its own input bias point. An example of input sensitivity of the prescaler input buffer is shown below in figure 8.
An example of prescaler input impedance is shown below in figure 9.
Prescaler / VCO divider
All Super PLLs divide the VCO signal using a prescaler, which is a bipolar circuit in all devices with the exception of the 'C' series. In all devices with the exception of the MB15U10, the prescaler has at least two dividing ratios (hereafter known as P and P+1). This type of prescaler is known as dual modulus. The dividing ratio of this initial prescaler defines the minimum channel spacing achievable (together with the reference divider). The prescaler is followed by a CMOS counter, (hereafter referred to as the N-counter), which divides the signal further to the comparison frequency of the phase detector. When in lock, the frequencies at the phase detector are equal. In a single modulus system the generated frequency is then given by
fvco =fref (N.P/R).
In a dual modulus system the prescaler divider ratio is dynamically altered during the course of an (R/fref ) period. This altering is achieved by the use of a controlling swallow counter (hereafter known as the 'A' counter). The value of the A counter is programmed via the serial interface, to a value less than that of the N counter. At the start of a (R/fref ) or (N/fvco ) period, the prescaler will divide by the dividing ratio (P+1), until the A counter reaches its programmed value. Thereafter the prescaler will divide by P. This leads to the following formula, which defines the frequency generated.
fvco =fref (NP+A)/R.
A dual modulus system can be used as single modulus by simply setting the 'A' value to 0. Most Super PLLs have two pairs of moduli, which can be statically selected via the programming interface. In the example of MB15E07L the prescaler can be configured as either 32/33 or 64/65. The N, A and R counters have wide programming ranges to enable use in a wide variety of applications.
Charge pump / phase detector
The divided VCO and reference signals are applied to the phase detector, in order to produce an error signal, which is then fed to the balanced current source charge pump. The phase detector is of type 4, i.e. a phase/frequency detector. This means that when the loop is very far from lock, frequency is compared until both signals are equal before phase is compared. The Fujitsu Super PLL series features a proprietary architecture, the supercharger, which allows excellent phase noise performance, low spurious output, coupled with fast channel-hop lock-in times. The supercharger charge pump is of balanced current source type, and the approximate circuit topology is depicted in Figure 10. A typical example of the static output currents varying with applied voltage on the output can be seen in figure 11.
Figure 10: Charge pump topology
