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Added features of particular PLL series

The 'E' Series

P/No. fin (max Hz) P Divide ratio N. counter. A. counter. R. counter. Vcc 2.7..3.6V (Icc,typ) Feature PKG
MB15E03L 1.2G 64/65
128/129
5 to 2047 0 to 127 5 to 16383 2.5mA PS/ZC 16SSOP
MB15E05L 2.0G 4mA
MB15E06 2.5G 8mA
MB15E07L 2.5G 32/33
64/65
4.5mA

The 'E' series of PLL has two added features; a hardware power save (PS) controlled from a single pin, and a hardware charge pump output tristate also controlled from a single pin (ZC). The former enables the switching of the PLL in and out of its standby status without it being necessary to access the 3-wire bus, thus saving time (and therefore power) when switching. The latter enables the user to switch the charge pump into a high impedance mode which is useful for open loop modulation schemes where the VCO is set to a particular frequency, and the loop opened to allow the VCO to run free. This places a high requirement on the leakage current of the components connected to the tuning pin on the VCO, i.e. the loop filter capacitors must have a very high series resistance, as must the tristated charge pump. The ZC pin enables this high impedance mode without the requirement to access the 3-wire bus, thus allowing faster switching between channels. The 'E' series also features a separate charge pump power supply pin (Vp). This allows the user to operate the digital part of the PLL device at 3V, thus saving power, whilst operating the analogue part at a higher voltage to enable a greater VCO tuning range, with no power consumption penalty. The Vp pin must be operated at a voltage greater than or equal to Vcc and less than 6V. The 'E' series is available in 16 pin SSOP and 16 pin BCC-S packages.

The MB15-F series

P/No. fin (max Hz) P Divide ratio N. counter. A. counter. R. counter. Vcc 2.7..3.6V (Icc,typ) Feature PKG
MB15F02/L 1.2G 64/65
128/129
5 to 2047 0 to 127 5 to 16383 6mA/4mA PS 16SSOP
16BCC-D
500M/
250M
16/17
32/33
MB15F03/L 2.0G 64/65
128/129
9mA/5mA
500M/
250M
16/17
32/33
MB15F05L 2.0G 64/65
128/129
4.5mA 16SSOP
16BCC-D
233.15M fixed fixed fixed fixed 5mA
MB15F06 2.0G 64/65
128/129
5 to 2047 0 to 127 5 to 16383 9mA
300M 8/9
16/17

The 'F' series is a series of dual channel PLLs. The channels are split into two separate frequency areas, an 'RF' channel for the generation of a 1st LO, and an 'IF' channel for the generation of a 2nd LO. This makes the 'F' series ideal for double superhet radio systems. The 'F' series is available in 16 pin SSOP and 16 pin BCC-D packages. As pin count is limited for a dual PLL, a single pin reference input, power save (PS) pin for each channel, and a single power supply for each channel are provided.

The MB15C Series

P/No. fin (max Hz) P Divide ratio N. counter. A. counter. R. counter. Vcc 2.7..3.6V (Icc,typ) Feature PKG
MB15C02 220M/1.0V 64/65 5 to 4095 0 to 63 16 to 16383 1.5..2.0mA PS 16/20SSOP
330M/1.2V
MB15C03 90M/1.0V 64/65 5 to 4095 0 to 63 16 to 16383 0.5..0.7mA PS 16SSOP

The 'C' series of PLL comprising MB15C02 and MB15C03, represent Fujitsu's offering for low voltage applications. They are constructed in a low threshold voltage pure CMOS process, which enables operation down to a power supply voltage of 1V. The prescaler is also constructed in CMOS, meaning that the frequency range on offer makes the parts suited to Pager applications such as the European POCSAG and ERMES standards. The MB15C02 features a power saving mode controlled by a PS pin. The MB15C02 will operate from a single 1.0V supply, meaning that single battery cell operation is possible without the use of a DC/DC converter. The MB15C02 is available in 16 or 20 pin SSOP. The MB15C03 also features a power saving mode controlled by a single pin, but in this case a separate charge pump power supply pin is available. This enables a larger tuning range VCO to be used while still maintaining low power consumption, with the digital part of the PLL, in a similar fashion to the 'E' series devices. The MB15C03 is available in a 16 pin SSOP package.