After discussing the architecture of Fujitsu PLLs and special features of particular series, this application note describes the calculation of a loop filter, then gives practical advice on RF layout for good results, including design of an evaluation system to aid development of reliable frequency synthesiser loops.

A list of recommended texts is included.

The next article details application benchmark designs for the GSM, DECT and DCS1800 standards concluding with typical results for these systems.

Pictured is the block diagram depicting the architecture of a typical Fujitsu Super PLL, the MB15E07L.

As can be seen, all of the features of the simplified block diagram are present. All parts in the same series have an identical architecture, and all super PLLs in the current Fujitsu product offering have similar architectures with minor differences.

Reference oscillator

All super PLL devices have an input port to provide the PLL with a reference signal. In the example below there is an internal oscillation circuit which can be configured as an input buffer amplifier as shown in figure 3, or as a crystal oscillator as shown in figure 4.

In the diagram in figure 3, the reference source is shown AC coupled to the input pin OSC_in, while the output pin OSC_out is left open. Direct coupling is also possible but requires that the reference source exceeds the threshold of the input buffer. As the average DC bias level of the reference source will be different from the threshold level, the duty cycle of the reference signal at the output of the internal buffer will not be 50/50. This will affect the synthesiser performance. In the diagram in figure 4, the internal oscillation buffer generates the reference signal for the PLL with the external capacitors and crystal defining the output frequency. Care should be taken to minimise the size of the capacitors to ground including the strays caused by the PCB, and the load due to the input capacitance of the crystal. It is not recommended that the total load on each pin exceed 20pF. The values of C1 and C2 are generally recommended by the crystal manufacturer.

Several devices (All 'F' series, All 'S' series) feature only a reference input pin due to package size limits, therefore only the configuration shown in figure 3 is possible, a typical representation of the reference input frequency range and sensitivity, when used in this manner is pictured in figure 5 below.

An example of the input impedance of the input buffer is pictured in figure 6.

VCO input buffer

The VCO input is applied to the IC through a high frequency differential buffer as shown in figure 7. The output level of the VCO can be attenuated to the minimum level required to stimulate the input buffer. It is always preferable to operate close to the minimum level as it helps minimise crosstalk in particular to the tuning point of the VCO, which could cause unnecessary spurii on the generated high frequency output signal. The capacitor to ground can be omitted with a loss of input sensitivity. AC coupling is required as the input buffer generates its own input bias point. An example of input sensitivity of the prescaler input buffer is shown below in figure 8.

An example of prescaler input impedance is shown below in figure 9.

Charge pump / phase detector

The divided VCO and reference signals are applied to the phase detector, in order to produce an error signal, which is then fed to the balanced current source charge pump. The phase detector is of type 4, i.e. a phase/frequency detector. This means that when the loop is very far from lock, frequency is compared until both signals are equal before phase is compared. The Fujitsu Super PLL series features a proprietary architecture, the supercharger, which allows excellent phase noise performance, low spurious output, coupled with fast channel-hop lock-in times. The supercharger charge pump is of balanced current source type, and the approximate circuit topology is depicted in Figure 10. A typical example of the static output currents varying with applied voltage on the output can be seen in figure 11.

The 'C' series of PLL comprising MB15C02 and MB15C03, represent Fujitsu's offering for low voltage applications. They are constructed in a low threshold voltage pure CMOS process, which enables operation down to a power supply voltage of 1V. The prescaler is also constructed in CMOS, meaning that the frequency range on offer makes the parts suited to Pager applications such as the European POCSAG and ERMES standards. The MB15C02 features a power saving mode controlled by a PS pin. The MB15C02 will operate from a single 1.0V supply, meaning that single battery cell operation is possible without the use of a DC/DC converter. The MB15C02 is available in 16 or 20 pin SSOP. The MB15C03 also features a power saving mode controlled by a single pin, but in this case a separate charge pump power supply pin is available. This enables a larger tuning range VCO to be used while still maintaining low power consumption, with the digital part of the PLL, in a similar fashion to the 'E' series devices. The MB15C03 is available in a 16 pin SSOP package.

The complete structure of the loop filter creates a fourth order loop (third order filter, the extra pole is created by the nature of the PLL). The components R0 and C0 represent the core of the loop filter, whereby the other components, C1, and the cascaded low pass R2 and C2, are employed to further enhance the system performance by adding higher order attenuation. The low pass filter may be omitted in many applications. In the optimisation of any PLL frequency synthesiser, there are three main considerations. Each factor has an influence on the selection of the loop bandwidth. The first factor is the selection of maximum available loop bandwidth to achieve minimum hopping time between two frequencies (for a channelised system). The second is the selection of minimum loop bandwidth for maximum suppression of reference sidebands in the output frequency spectrum. The third is the optimum selection of loop bandwidth for the minimum phase noise generated by the PLL. As the order of the loop increases the calculation of the loop filter components becomes cumbersome. In the following calculation method only the components R0 and C0 are generated from a theoretical approach, C1 is generated by a simple rule of thumb, and the low pass filter can be dimensioned to have a 3dB cutoff approximately a decade away from that of the loop bandwidth.

First of all the designer must specify his system. This example assumes a channelised system of which locking time is the most critical. This is applicable to any FDMA/TDMA based radio standard. Specification of hopping time requires the definition of three parameters:

• f_a (Hz) - frequency accuracy to desired frequency, i.e. how close the carrier must be to the desired frequency when hopping time is measured.
• f_step (Hz) - frequency hopping step, taken from the lowest frequency required in the radio system to the highest required.
• T (s) - hopping time, the maximum allowable time taken to switch between the channels farthest apart. As a rule of thumb, the highest lock speed achievable with conventional, i.e. non-fractional-N dual modulus systems is around 300microseconds.

Taking E-GSM as an example, let FA =1kHz, f_step =880-960=80MHz and T=450µs. Two parameters can be extracted from data supplied by the manufacturers of the components used:

• K_v (Hz/V) - the conversion gain of the VCO employed.
• I_cp (mA) - the DC charge pump current as measured at the output. Measurement conditions are usually specified as being the current drawn to ground or supply when the voltage on the charge pump output is held at midrail.

If the charge pump currents are not equal, then the complete gain is calculated by adding the modulus of the positive source to that of the negative source and dividing by two.

The channel spacing of the system must also be selected. This implies also the maximum frequency at which the phase detector can resolve phase differences between the two signals. It is desirable to make the phase detector operate at this frequency as, the higher the reference frequency, the lower the phase noise that will be generated on the carrier, furthermore no reference spurious will be generated within the loop bandwidth. When the channel spacing is decided, the mean N divider ratio can be calculated. Taking the approximate midband frequency, and dividing by the channel spacing results in the average N counter setting. For example...

E-GSM band, bottom channel, 880MHz, top channel 960MHz, midband 920MHz. The IF must then be subtracted (for low side injection) from this frequency 920MHz-246MHz = 674MHz. Channel spacing 200KHz,

N = 674 X 10⁶ /200 X 10³

N = 3370.

In this case N represents the combined N (programmable divider) and P (prescaler) divide ratios. It doesn't matter if the resulting number is not a factor of the smallest prescaler dividing ratio, as the exact division ratios are taken care of by the dual modulus control logic.

Now we come to our first calculation, the natural frequency of the loop.

The following formula can be used to calculate f_n :-

f_n = (-1/(2π*T*ζ)).ln(FA /f_step ).

Where z is the damping factor of the loop. For this calculation, damping factor is chosen as 0.7. For a theoretical derivation of such a formula set, see the recommended texts listed at the end of this section. Subsequent to the calculation of fn , the component value can be calculated as follows:-

C0= I_cp *kV /(N(2π f_n )2)

R0 = √(N/(I_cp kV C0))2ζ

C2 can be approximated as C0/10.

If a more accurate calculation is required of the full 3rd or 4th order loop then computer methods should be employed.

• Frequency Synthesiser Design Handbook: James A. Crawford, (Artech House)
• Phaselock Techniques: F.M. Gardner, (John Wiley and Sons)
• Digital PLL Frequency Synthesisers Theory and Design: U.L. Rohde, (Englewood Cliffs)

In order to obtain a reliable and high performance RF design, several PCB layout guidelines must be followed. RF signal lines should be kept as short as possible, and where possible with 50 ohm terminations, this is relatively easy to realise when using a multilayer board.

Careful decoupling of the power supplies is also important. In addition to the usual large decoupling capacitors, smaller devices should also be placed as close as possible to the power supply pins. These devices act as a low impedance path to ground for any stray high frequency transients. Normally a value of around 100pF can be employed for this purpose.

The connections between the AC ground and the decoupling structures should be laid out as a ground plane in order to avoid the generation of stray inductance which can negate the effect of the capacitances, or worse still generate a resonant circuit which can lead to parasitic oscillations. Contacting to the ground plane from the bond pin, leads in general to an inductance of 1nH, therefore as many vias as possible should be employed. As a rule the synthesiser supply should be separated from any digital circuitry also present in the design.

Particularly sensitive is the ground connection to the loop filter. This ground should be properly decoupled from the charge pump output, and from the VCO. To achieve the best performance, the loop filter should be constructed from film capacitors, which exhibit a high Q factor, i.e. low series resistance.

Measurement hints

When measuring it is preferable to use a shielded chamber. A low noise signal generator or the actual TCXO from the system to be designed must be used for the OSCin signal. Ground loops can create 50Hz spurious and harmonics around the carrier signal. Some measurement instruments, especially those equipped with a cathode ray display, can generate higher frequency spurii. For a test setup, additional inductors in the power rails can improve the noise peformance. For phase noise measurements, all generators should be connected to the same reference timebase.