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PCS1900 Application Benchmarks

 3. PCS1900 Low side injection
Figure 31. Application circuit, PCS1900 low side injection

Figure 31. Application circuit, PCS1900 low side injection


This was simulated under the following conditions:-

VCC 3.0 V
V CP, V VCO 4.6 V
Comparator frequency 200 kHz
Prescaler divide ratio 32/33
Reference oscillator 13 MHz, -3 dBm
RF out 1767 MHz
Ambient temperature 25°C
VCO Murata MQE 520-1767(Kv = 31 MHz/V)

Parts list:

C1 100 pF
C2 10 nF
C3 10 µF
C4 100 pF
C5 33 pF
C6 33 pF
C10 100 pF
C11 10 µf
R3 0 Ω
R4 51 Ω
R5 47 κΩ
R6 47 κΩ
R7 47 κΩ
R8 18 Ω
R9 18 Ω
R10 18 Ω

Loop filter:

C7 3.3 NF
C8 33 NF
C9 220pF
R1 12 κΩ
R1 1.2 κΩ

Test results

Spurious performance @Δf = 200 kHz @Δf = 400 kHz @Δf = 600 kHz @Δf = 13 MHz
@1767 MHz -65.6 dBc -76.0 dBc -83.5 dBc -67 dBc
Phase noise performance Measured value Unit Remarks
@1767 MHz -71.8 dBc/Hz maximum within loop bandwidth = 12.5 kHz
Phase error RMS value Peak value Unit
@1767 MHz 2.3 6.5 degrees
Hopping time Measured value Unit Remarks
1737 MHz → 1797 MHz 466 µs  
1797 MHz → 1737 MHz 466 µs  
Figure 32 - Spurious performance at 1767 MHz -65.6 dBc

Figure 32 - Spurious performance at 1767 MHz -65.6 dBc

Figure 33 - Phase noise performance; C/N= -71.8 dBc/Hz, maximum within loop bandwidth

Figure 33 - Phase noise performance; C/N= -71.8 dBc/Hz, maximum within loop bandwidth

Figure 34 - Phase noise performance @ Δ f= 1MHz from carrier; C/N= -139.3 dBc/Hz « -146.3 dBm/Hz

Figure 34 - Phase noise performance @ Δ f= 1MHz from carrier; C/N= -139.3 dBc/Hz « -146.3 dBm/Hz

Figure 35 - Phase noise performance @ Δ f= 10 MHz from carrier; C/N= -147.6 dBc/Hz « -154.6 dBm/Hz (close to measurable limit)

Figure 35 - Phase noise performance @ Δ f= 10 MHz from carrier; C/N= -147.6 dBc/Hz « -154.6 dBm/Hz (close to measurable limit)

Figure 36 - Hopping time 466µs for frequency step 1737MHz → 1797MHz (Measurement triggered 100µs after PLL was programmed, therefore the marker readout shown on top is 100µs longer than the actual hopping time)

Figure 36 - Hopping time 466µs for frequency step 1737MHz → 1797MHz (Measurement triggered 100µs after PLL was programmed, therefore the marker readout shown on top is 100µs longer than the actual hopping time)

Figure 37 - Hopping time 466µs for frequency step 1797MHz → 1737MHz (Measurement triggered 100µs after PLL was programmed, therefore the marker readout shown on top is 100µs longer than the actual hopping time)

Figure 37 - Hopping time 466µs for frequency step 1797MHz → 1737MHz (Measurement triggered 100µs after PLL was programmed, therefore the marker readout shown on top is 100µs longer than the actual hopping time)

Figure 38 - Phase error @1767MHz, RMS value: 2.3°, peak value: 6.5°

Figure 38 - Phase error @1767MHz, RMS value: 2.3°, peak value: 6.5°