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GSM Application Benchmarks

 1. GSM High Side Injection
Figure 15 Application circuit, GSM high side injection

Figure 15 Application circuit, GSM high side injection


GSM 1st LO high side injection was simulated with the following design conditions.

VCC 3.3 V
V CP, V VCO 5 V
Comparator frequency 200 kHz
Prescaler divide ratio 64/65
Reference oscillator 13 MHz, -3 dBm
RF out 1018 MHz
Ambient temperature 25°C
VCO Murata MQE 042-1016 (Kv = 20 MHz/V)

Parts list:

C1 100 pF
C2 10 nF
C3 10 µF
C4 100 pF
C5 33 pF
C6 33 pF
C10 100 pF
C11 10 µf
R3 0 Ω
R4 51 Ω
R5 47 κΩ
R6 47 κΩ
R7 47 κΩ
R8 18 Ω
R9 18 Ω
R10 18 Ω

Loop filter:

C7 2 nF
C8 20 nF
C9 330 pF
R1 15 κΩ
R2 2.2 κΩ

Test results

Spurious performance @Δf = 200 kHz @Δf = 400 kHz @Δf = 600 kHz @Δf = 13 MHz
@1018 MHz -83.2 dBc -94.5 dBc -100.0 dBc(1) -100.0 dBc(1)
Phase noise performance Measured value Unit Remarks
@1018 MHz -71.0 dBc/Hz maximum within loop bandwidth = 20.5 kHz
@Δf =1 MHz from carrier -139.3 dBc/Hz  
@Δf =1 MHz from carrier -146.3 dBm/Hz  
@Δf =10 MHz from carrier -147.6(1) dBc/Hz(1)  
@Δf =10 MHz from carrier -154.6(1) dBm/Hz(1)  
Phase error RMS value Peak value Unit
@1018 MHz 2.2 6.8 degrees
Hopping time Measured value Unit Remarks
1005 MHz → 1031 MHz 486 µs  
1031 MHz → 1005 MHz 427 µs  
Close to measurable limit
Figure 16 - Spurious performance at 1018 MHz

Figure 16 - Spurious performance at 1018 MHz

Figure 17 - Phase noise performance; C/N= -71.0 dBc/Hz, maximum within loop bandwidth

Figure 17 - Phase noise performance; C/N= -71.0 dBc/Hz, maximum within loop bandwidth

Figure 18 - Phase noise performance @ Δ f= 1MHz from carrier; C/N= -139.3 dBc/Hz « -146.3 dBm/Hz

Figure 18 - Phase noise performance @ Δ f= 1MHz from carrier; C/N= -139.3 dBc/Hz « -146.3 dBm/Hz

Figure 19 - Phase noise performance @ Δ f= 10 MHz from carrier; C/N= -147.6 dBc/Hz « -154.6 dBm/Hz (close to measurable limit)

Figure 19 - Phase noise performance @ Δ f= 10 MHz from carrier; C/N= -147.6 dBc/Hz « -154.6 dBm/Hz (close to measurable limit)

Figure 20 - Hopping time 486µs for frequency step 1005MHz → 1031MHz (Measurement triggered 100µs after PLL was programmed, therefore the marker readout shown on top is 100µs longer than the actual hopping time)

Figure 20 - Hopping time 486µs for frequency step 1005MHz → 1031MHz (Measurement triggered 100µs after PLL was programmed, therefore the marker readout shown on top is 100µs longer than the actual hopping time)

Figure 21 - Hopping time 427µs for frequency step 1031MHz → 10305MHz (Measurement triggered 100µs after PLL was programmed, therefore the marker readout shown on top is 100µs longer than the actual hopping time)

Figure 21 - Hopping time 427µs for frequency step 1031MHz → 10305MHz (Measurement triggered 100µs after PLL was programmed, therefore the marker readout shown on top is 100µs longer than the actual hopping time)

Figure 22 - Phase error @1018MHz, RMS value: 2.2°, peak value: 6.8°

Figure 22 - Phase error @1018MHz, RMS value: 2.2°, peak value: 6.8°