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 Introduction |  GSM |  DECT |  PCS1900 |


DECT Application Benchmarks

 2. DECT Low side injection
Figure 23. Application circuit, DECT low side injection

igure 23. Application circuit, DECT low side injection


This was simulated under the following conditions:-

VCC 3 V
V CP, V VCO 4.6 V
Comparator frequency 1728 kHz
Prescaler divide ratio 32/33
Reference oscillator 27.648 MHz, -3 dBm
RF out 1776.384 MHz
Ambient temperature 25°C
VCO Murata MQE 520-1767 (Kv = 31 MHz/V)

Parts list:

C1 100 pF
C2 10 nF
C3 10 µF
C4 100 pF
C5 33 pF
C6 33 pF
C10 100 pF
C11 10 µf
R3 0 Ω
R4 51 Ω
R5 47 κΩ
R6 47 κΩ
R7 47 κΩ
R8 18 Ω
R9 18 Ω
R10 18 Ω

Loop filter:

C7 22 nF
C8 220 nF
C9 1.5 nF
R1 1.8 κΩ
R2 150 κΩ

Test results

Spurious performance @Δf = 200 kHz @Δf = 400 kHz @Δf = 600 kHz @Δf = 13 MHz
@1776.384 MHz -70 dBc -70 dBc -70 dBc(1) -72.5 dBc(1)
Phase noise performance Measured value Unit Remarks
@1776.384 MHz -80.5 dBc/Hz maximum within loop bandwidth = 13 kHz
Phase error RMS value Peak value Unit
@1776.384 MHz 1.0 2.4 degrees
Hopping time Measured value Unit Remarks
1769.472 MHz → 1785.024 MHz 388 µs  
1785.024 MHz → 1769.472 MHz 388 µs  
Close to measurable limit
Figure 24 - Spurious performance at 1776.384 MHz -70.0 dBc

Figure 24 - Spurious performance at 1776.384 MHz -70.0 dBc

Figure 25 - Phase noise performance; C/N= -80.5 dBc/Hz, maximum within loop bandwidth

Figure 25 - Phase noise performance; C/N= -80.5 dBc/Hz, maximum within loop bandwidth

Figure 26 - Phase noise performance @ Δ f= 1 MHz from carrier; C/N= -139.3 dBc/Hz ⇔ -146.3 dBm/Hz

Figure 26 - Phase noise performance @ Δ f= 1 MHz from carrier; C/N= -139.3 dBc/Hz ⇔ -146.3 dBm/Hz

Figure 27 - Phase noise performance @ Δ f= 10 MHz from carrier; C/N= -147.6 dBc/Hz « -154.6 dBm/Hz (close to measurable limit)

Figure 27 - Phase noise performance @ Δ f= 10 MHz from carrier; C/N= -147.6 dBc/Hz « -154.6 dBm/Hz (close to measurable limit)

Figure 28 - Hopping time 388µs for frequency step 1769.472MHz → 1785.024 MHz (Measurement triggered 100µs after PLL was programmed, therefore the marker readout shown on top is 100µs longer than the actual hopping time)

Figure 28 - Hopping time 388µs for frequency step 1769.472MHz → 1785.024MHz (Measurement triggered 100µs after PLL was programmed, therefore the marker readout shown on top is 100µs longer than the actual hopping time)

Figure 29 - Hopping time 427µs for frequency step 1785.024MHz → 1769.472MHz (Measurement triggered 100µs after PLL was programmed, therefore the marker readout shown on top is 100µs longer than the actual hopping time)

Figure 29 - Hopping time 427µs for frequency step 1785.024MHz → 1769.472MHz (Measurement triggered 100µs after PLL was programmed, therefore the marker readout shown on top is 100µs longer than the actual hopping time)

Figure 30 - Phase error @1776.384MHz, RMS value: 1.0°, peak value: 2.4°

Figure 30 - Phase error @1776.384MHz, RMS value: 1.0°, peak value: 2.4°