Contents |  General |  MB86060 16-bit 100MSa/s Interpolating DAC |  MB86061 12-bit 400MSa/s (ECL i/p) DAC |  Application Questions |  Glossary |

---

4.1: What is the recommended analog output configuration?

The performance of the DAC is largely determined by the configuration of the analog output stage. A particular output configuration should be selected depending on the required output levels. The various differential to single-ended output configurations are described in brief below.

4.1.1: Using transformers (ac differential coupling)

Note that a doubly terminated interface (load resistors located on primary and secondary sides of the transformer) is recommended when connecting to test equipment via cables. This is less critical in a final application where the DAC may be driving a filter or mixer a short distance away on a PCB.

Doubly terminated interface 1: Standard output similar to datasheet (p. 28, v 1.1, June 00). This is a two-stage transformer circuit giving good CMRR. The transformers recommended are Mini-Circuits ADTT1-1 and transmission line transformer ADTL1-12. The first (DAC source) and second (test equipment) terminations have equivalent load values (50 ohm). The RC filter in circuit provides constant load impedance to the DAC (corrects for transformer leakage inductance). Output power is -2dBm and Vpk is ± 250 mV for full scale output (20 mA).

4.2: What is the best configuration for maximising output power?

Increased output swing at the DAC output can cause increased distortion especially for single-tone generation. This is due to a weak dependence of output switch delay on output voltage which mainly affects third harmonic (IP3). This effect is most significant for large output signals. Since the DAC has a current output, voltage swing is proportional to load resistance. Doubling load resistance doubles voltage swing at the DAC output giving +3dB output power.

Comparing measurements in a doubly terminated 50ohm system, it was found that compared to a 1:1 transformer (e.g. ADTT1-1, -2dBm full scale, used in DK), a 2:1 impedance ratio transformer (e.g. ADT2-1T, +1dBm full scale) degraded third harmonic for a full-scale sinewave by a couple of dB.

Utilising the doubly terminated interface 3 above will increase the output power by about 1 dBm over the standard configuration. Output power is increased to about -1 dBm.

4.3: How are BGAP, VREF and RREF used?

Answer:

4.3.1 External voltage reference.

When using an external voltage reference, BGAP should be decoupled to the reference ground plane (RVSS) using a surface mount 100 nF capacitor. Decoupling is necessary to prevent noise pickup on the BGAP output which could feedback internally to the BGAP circuit. The external voltage reference is applied to VREF.

4.3.2 Internal voltage reference.

Using the internal Bandgap Reference:

1. The BGAP pin (bandgap output) should be linked to VREF (voltage reference input) via a 50 ohm (or less) resistor.

2. The VREF pin should be decoupled to Reference Ground (RVSS) via a 100nF capacitor.

4.4: What factors can lower SFDR values during testing?

1. High shuffle clock rates can cause distortion especially when generating low frequency signals. The trade-off is that low shuffle clock rates give reduced spreading out of distortion components.
2. Generating a full scale signal (0 dBFS) when using the dither function can cause clipping of the signal. (About 0.4 dB headroom is required for the lowest dither setting). The OVER pin should be monitored to check this.
3. Using the clock multiplier function can lower performance.
4. When using interpolation filters with input data peaking at full-scale, the interpolated data can exceed DAC full-scale and will be clipped. The OVER pin should be monitored to check this.

4.5: What are the critical issues regarding PCB layout for the DAC?

1. For differential clock input circuits, the transformer should be situated close to the DAC so that the PCB tracking is kept as short as possible. (Tracks should be 25 ohm impedance, but 50 ohm is acceptable with short track lengths).
2. Power supply noise should be kept to an absolute minimum (less that 10mV) to the analog, reference and clock supplies, as any supply variation will produce clock input to analog output delay variations. This will cause phase modulation on the DAC output, which will tend to dominate the output amplitude changes (amplitude modulation) with output frequencies > 1MHz. A very low impedance supply should be used for these blocks, with as much decoupling as possible.
3. Power supply tracks should be kept as short and wide as possible. Ground and supply tracks should run adjacent to each other as much as possible.

4.6: Can the input clock be driven with an ac coupled differential ECL/PECL signal?

Yes. With AC coupling, all that is required is correct biasing for CMOS (for the MB86060) or ECL/PECL (for the MB86061).

4.7: Is there a minimum sampling rate?

For the MB86060, it depends on whether the clock multiplier is enabled or bypassed: Clock multiplier enabled: input clock > 10 MHz, multiplication factor such that DAC clock > 40 MHz.

Clock multiplier bypassed: no minimum clock frequency. Note that if the DAC is operated at very low frequencies, the analog output interface may require some special consideration. The differentially coupled transformer circuit can be replaced with an op amp circuit (see section 4.1.2 above) to obtain performance down to dc. Alternatively, using the Mini-circuits ADTL1-4-75 as the line transformer gives improved CMRR and distortion at low frequencies (< 30 MHz).

NOTE: The ADTT1-1 and ADT1-1WT transformers show increased 3rd harmonic distortion at 1 MHz or below. For lower frequency signals, use a more suitable transformer.

4.8: Is there any required power-on sequencing for the power rails?

No, there is no required sequence. This is helped by Fujitsu's triple well structure where the different power domains are in separate wells and the substrate is grounded. The only requirement is that a FULL-RESET is performed after power up.

4.9: Can high frequency IF images be accessed directly with the DAC?

There are different definitions of IF. Technically, a single carrier wideband WCDMA channel that can be generated with the MB86060 (centred at 16 or 32 MHz) is an IF image. The FME DAC demonstrates superior performance in this area (reference ACPR figures).

This region is slightly offset from baseband, but is it possible to band-pass filter the output of the DAC to select a higher order image (up around 100 - 150 MHz)? If this is possible, the advantage to the system designer is to avoid the first mixer stage of the IF/RF up-conversion. With the MB86060 Interpolating DAC, it is theoretically feasible to access these images using the x2 fast mode, but it would require the system designer to design in a digital high pass filter prior to the DAC.

One potential DAC solution would be to utilise a switchable low-pass/high-pass filter and zero-stuffing. With a single x2 interpolation filter in high pass mode, it is feasible to target these higher images. There are two major drawbacks. One is inherent in any DAC which is the absolute analog performance. This tends to degrade quite sharply at higher frequencies. Secondly, utilising zero-stuffing along with the high-pass filter will allow you to select the higher images within a flatter passband but the trade-off is a significant reduction in signal output power.

The ideal solution would be a true x4 interpolation DAC with both filters being switchable for low-pass/high-pass to create a true bandpass filter.

4.10: Why is splitting of power and ground planes recommended?

Power and ground planes should be split to isolate the digital, clock and analog regions of the circuitry to prevent supply noise coupling from one to another. There are two types of power/ground splits recommended. One is separation of the clock, reference, signal and digital sections and the second is isolation of the digital data interface from the digital control section.

4.10.1 Clock, reference, signal, and digital power/ground splits

The clock, reference, analog and digital sections are all separated inside the chip (power and ground) and internally decoupled. The digital filters, noise shaper, ditherer, and decode logic all run off internal digital supply. These all take code-dependent transient current out of the supply (and into ground). Even with on-chip and off-chip decoupling, this current must be prevented from affecting the analog/clock and so power/ground plane isolation is recommended.

The analog part of DAC (output switches and drivers) takes transition-dependent current; if this gets into clock path supply/ground it can cause delay modulation and if it gets into reference circuit supply/ground it can cause amplitude modulation. Both effects degrade SFDR, so the analog output section is separated on-chip from clock and reference circuits. Once these have been decoupled (low impedance shunt at high frequency), they can all be connected to the same power supply, preferably through small inductors (series isolation).

4.10.2 Digital data interface power/ground split

It is also recommended that the digital supply and ground planes be split further to isolate the digital control and data blocks. The digital data region connects to the application circuit and as such will be subject to significant noise.

When using a remote data generator (e.g. a benchtop pattern or data generator) there is a tendency for noise to be injected on the data ground by the equipment. Wide data buses with fast rise/fall times cause large data-dependent transient currents to flow from the data source. These currents travel along the PCB tracks, through chip package/pad parasitics and decoupling capacitors, and back along the ground plane to the data source. Since this current flows from an external source, decoupling (on or off chip) doesn't help. This causes common-mode noise at chip data input pins which is isolated from the rest of the chip by an internal triple-well structure (separate supply and ground). If this noise gets into clock circuits it causes data-dependent jitter which degrades SFDR. If it gets into the analog circuits it can appear at the output unless CMRR is very high.

Circulating currents in ground plane must not pass into analog region of PCB.It is recommended that a "U-shaped" cut be made in power/ground planes with the open end at data source, the I/O powered from this region and all I/O decoupling inside it. All the data return currents will then be confined inside this "U" so none of them can couple into the analog ground plane to degrade SFDR.

4.11: What heat sinking measures are recommended?

Heat dissipation will occur naturally via convection to the air surrounding the board and via conduction to the PCB. Additional heat sinking may be required depending on clock rate and output level. Various methods can be used but consideration must be given to the constraints of space and amount of air circulation. Several methods are outlined below.

4.11.1 Bonded heat sink

A metallic-fin heat sink can be bonded directly to the chip package with thermally conductive adhesive.

4.11.2 Using the PCB as a primary heat sink

The material used in the manufacture of the PCB will also have a major effect upon the performance of the PCB as a heat sink. Where an FR-4 epoxy glass laminate PCB is used, an area of approximately 26cm² will be required to dissipate 1 watt, but materials specifically designed for thermal management applications can achieve an equivalent dissipation over an area as small as 6cm².

4.11.3 Heat transfer through a PCB mounted heat shunt

The PCB can alternatively be used to transfer heat directly into a heat sink. This can be done by providing a thermal path from the underside of the package, through the PCB and into a heat shunt attached to the reverse side. This heat shunt can then conduct the heat into a fixed heat sink, which could be external to the enclosure, or even the case itself. Heat will be transferred from the package into the PCB via a thermally conductive joint placed between the underside of the package and the PCB. The thermal conductivity of the PCB under the package is further improved by a series of plated through holes, which conduct heat into a heat shunt. This provides an electrically non-conductive interface between the surface of the PCB and the heat sink.

4.11.4 Using a Remote Heat Exchanger

A Remote Heat Exchanger (RHE) utilises heat pipes to conduct heat away from the package to a suitably located heat sink. The heat pipe is attached to the device by a small thermal transfer plate, usually bonded to the package with an adhesive compound. The heat pipe is then routed across the enclosure to the heat sink attachment point, typically the system enclosure.

Typical heat pipes are capable of dissipating many Watts of heat. The heat pipe method of cooling has considerable advantages over the directly connected heat sink methods as it allows for much simpler system design. Special consideration for heat sinking into, and attachment to the PCB can be kept to a minimum. Multiple devices can be cooled using a single remote heat sink. For these reasons, heat pipes are the preferred method of cooling in many complex systems.

4.12: What are the critical issues with clock jitter (DLL vs. PLL)?

The DLL clock multiplier on the MB86060 can introduce both random jitter (wideband phase noise) and sidebands at multiples of the reference clock frequency (repetitive jitter). For low-jitter applications, the clock multiplier should be bypassed and an external reference clock used. The clock multiplier is provided mainly for user convenience in applications where performance is not so critical.

Comparing DLL to PLL circuits: For a DLL clock multiplier, close-in phase noise is very low. The oscillator used in the PLL circuit inherently introduces instability and an accumulation of phase error. Conversely, the unconditionally stable DLL architecture does not accumulate phase error. Although any integrated clock multiplier will always degrade phase noise, the delay-line based multiplier in the MB86060 is considerably better than a VCO-based multiplier (PLL).

A clock input slew rate of 0.5V/ns minimum is recommended for lowest phase noise (clock multiplier disabled).

4.13: What effect do the Segment Shuffling and Noise Shaping functions have on the noise floor/SNR?

Note that the test configuration will have a large influence on the results obtained. Noise from the spectrum analyser can contribute as much as 10 dB to the noise floor for certain test configurations. Correction factors for noise from measurement instruments should always be included. When measuring SNR for large signals, it is essential to filter out the fundamental and use a low noise analyser with no RF attenuation.

Using the noise shaping function results in an improved in-band noise floor level. With noise shaping off, noise is limited to the theoretical 12-bit level and truncation may appear as discrete spurs. When the second order noise shaping function is applied to data prior to being passed to the DAC core, an additional reduction in quantisation noise over that gained through the use of the interpolating filters. The relative decrease in noise floor (noise shaper off to on) depends upon generated signal level and test set-up. With noise shaping there is some noise contribution from the digital section which would limit SNR to a maximum value for ideal performance at small signal levels. As signal level increases other noise sources appear (such as reference current noise) resulting in a lower SNR.

The dynamic linearity (SFDR) of the DAC is improved with segment shuffling. The trade-off is that the overall noise floor is raised so the SNR goes down. The DAC INL (integral non-linearity) is converted into noise; the amount of noise generated depends on the exact non-linearity of each DAC.

4.14: When should the Dither function be utilised?

For best spurious performance on deterministic signals (e.g. one sinewave, particularly if the repeat period is short) and also for small signals it is recommended that the dither function be used. When both dither and noise shaping are used, there will generally be no discrete spurs above the noise floor other than those expected from harmonics caused by DAC INL. These will disappear for signals smaller than the dither amplitude. That is why dither is programmable; larger dither levels extend this spur-free region to higher amplitudes (at the cost of reducing maximum usable input level).

For modulated signals dither gives little or no improvement in SFDR since the input data is effectively self-dithered.

4.15: What impact does clock/data timing have on performance?

Other manufacturer's DAC's have shown significant variation in performance (SNR) relative to the clock to data timing. Thanks to the triple well structure, which isolates the digital I/O noise injection from the rest of the device, Fujitsu's DAC's don't exhibit this sensitivity to clock/data timing.

Such sensitivity to clock/data timing makes it very difficult for the system designer to guarantee the clock/data timing to sufficient accuracy (without manual set-up in production) in order to meet design tolerances for a final PCB design.

  Previous Page      1       2       3       4     5     6      Next Page