CHArge-mode Interleaved Sampler technology (CHAIS)

56 GSa/s 8-bit Analogue to Digital Converter (ADC)

Downloads

• Technology Backgrounder 56Gs/s ADC Enabling 100GbE (requires short registration)
• C60 - Factsheet LEIA DAC 55-65GSa/s 8-bit
• C63 - Factsheet LUKE-ES DAC 55-65GSa/s 8-bit
• C64 - Factsheet LUKE-DK/-SOCKET 55-65GSa/s 8-bit
• C45 - Factsheet CHAIS ADC 56GSa/s 8-bit Analog to Digital Converter
• C49 - Factsheet CHAIS Development Kit 56GSa/s 8-bit ADC
• ECOC Torino - Is smaller always better? ...as seen from a Network IC viewpoint
• OFC/NFOEC 2010 - 56Gs/s ADC Enabling 100GbE
• Reality Check: Challenges of mixed-signal VLSI design for high-speed optical communications

Fujitsu’s ultra-fast CMOS ADC enables upcoming telecommunication applications, such as 100G Ethernet and OTU-4 transport systems using coherent receivers. The ADC uses Fujitsu’s revolutionary Charge-mode Interleaved Sampler technology (CHAIS), which allows the implementation of extremely fast and high resolution ADCs in CMOS process technology.

Major benefits of the CHAIS ADC are low power consumption and the option to be integrated with millions of gates onto the same die using Fujitsu’s standard 65nm CMOS process technology. In combination with Fujitsu’s leading flip-chip packaging technology, the ultra-fast ADC is ideal for applications that require high performance analogue and huge digital processing power while maintaining a reliable and proven manufacturing flow.

56GSa/s 8-bit ADC development kit

Evaluation board

The 56 GSa/s ADC evaluation board (BATBOARD) allows early silicon characterisation of Fujitsu’s CHAIS (CHArge-mode Interleaved Sampler) ADC technology, and provides very fast data capture for high-speed signals. With two channels of 56GSa/s 8-bit ADCs packaged in a single ROBIN device, it provides unique features to simplify measurement and evaluation in the lab. It is ideal for prototyping next generation test and measurement systems as well as trials towards new communication technologies.

Two variants of the board are available. Version 1 has a device soldered down for maximum performance. Version 2 uses a low inductance socket which allows replacement of the device under test, with a small reduction in performance. Special attention has been given to the connector choice to allow connection to instrumentation that will perform the design verification tests. The board uses lowloss RF material to optimise the integrity of the signals.