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Process Technologies
CMOS technology
Fujitsu has extended its global semiconductor technology leadership with the introduction of world-class 65nm CMOS technology for ASIC and COT customers. Our 65nm technology shrinks gate length by 25 percent compared with 90nm technology, and provides a broad range of options for maximizing performance and minimizing power consumption.
Features of the 65nm technology include 30nm gate lengths, which is 25 percent smaller than the gate size for 90nm, CS100, transistors; speeds that are 20 percent to 30 percent faster than the speeds afforded using 90nm technology; transistor density that is doubled and SRAM cells that are only half the size of those delivered by 90nm technology.
In addition to digital gate complexities - suitable for million gates system-on-chip designs - most of Fujitsu's CMOS technologies offer mixed signal analogue integration based on triple well technology. Fujitsu's packaging technology supports designs from as low as 48 pins (e.g. BCC48) to high pin count BGA packages with up to more than 2000 balls. Information for our latest CMOS technology processes can be found here, if you have further questions please contact us.
65nm process PDF Presentation [1092kB] 
Key features
- Ultra-high-speed performance (CS200)
- LG = 30nm, on-current enhance
- Compared to 90nm technology, CS200 offers:
- 1.3 times faster speed
- 0.6 times lower power
- 2 times higher density
- 3 variations of Vth on a chip (CS200A)
- (1.8V & 2.5V) or (1.8V & 3.3V) I/O combination available
- 11-layer copper interconnects with robust, very low K ILD
90nm CMOS process
Features
- High integration
- Transistor of 80nm gate length (ITRS road map 90nm)
- 10-layer fine pitch, copper wiring, and low-k insulating material techniques
- Maximum 91 million gates (nearly twice that of 0.11μm technology)
- Low power consumption/low leakage current
- I/O with pad structure with fine pad pitch technology for chip size reduction
- Small gate propagation delay tpd = 12 ps (@1.2V, inverter, and F/O=1)
