FUJITSU

Mixed Signal

Besides Digital IP, today's systems require higher integration levels, including analogue functionality on the chip. Mixed signal chips can be designed by either using predefined analogue functions or by the custom development of complete complex analogue front-ends.

Fujitsu has a great deal of experience in mixed signal designing, and can utilise its mixed signal design centre in Maidenhead (UK) for customised designs.

A large analogue IP portfolio allows a building-block approach even for complex functionalities, or a 'pick and place' for more simple applications.

Examples of an analogue IP portfolio

  • ADC
  • DAC
  • OPamp
  • Comparators
  • PLLs / Clock multipliers

Further mixed signal IP blocks for ADCs, DACs and analogue cells have been developed, in addition to the IP blocks listed in the tables here.

For more information please contact asic-cot-info@fme.fujitsu.com.

DACs

180nm 130nm 90nm 65nm
8bit 200KS/s 6bit 54MS/s 8bit 300KS/s 8bit 300KS/s
8bit 300KS/s 6bit 100MS/s 8bit 1MS/s 8bit 1MS/s
8bit 1MS/s 8bit 300KS/s 10bit 300KS/s 10bit 300KS/s
8bit 50MS/s 8bit 1MS/s 10bit 1MS/s 10bit 1MS/s
8bit 80MS/s 8bit 12.5MS/s 10bit 54MS/s 10bit 45MS/s
10bit 300KS/s 8bit 50MS/s 10bit 110MS/s 10bit 54MS/s
10bit 1MS/s 10bit 300KS/s 10bit 220MS/s 10bit 110MS/s
10bit 40MS/s 10bit 1MS/s 12bit 54MS/s
10bit 50MS/s 10bit 54MS/s

10bit 80MS/s 10bit 150MS/s

10bit 110MS/s 16bit 96KS/s

12bit 110MS/s


ADCs

180nm 130nm 90nm 65nm
7bit 420MS/s 6bit 54MS/s 6bit 108MS/s 8bit 54MS/s
8bit 300KS/s 6bit 100MS/s 8bit 12.5MS/s 8bit 100MS/s
8bit 1MS/s 8bit 300KS/s 8bit 54MS/s 10bit 1MS/s
8bit 25MS/s 8bit 3MS/s 8bit 160MS/s 10bit 33MS/s
8bit 50MS/s 8bit 12.5MS/s 10bit 1MS/s 10bit 45MS/s
10bit 300KS/s 8bit 50MS/s 10bit 30MS/s 10bit 90MS/s
10bit 1MS/s 10bit 300KS/s 10bit 40MS/s 12bit 90MS/s
10bit 30MS/s 10bit 1MS/s 10bit 80MS/s
10bit 40MS/s 10bit 30MS/s 12bit 50MS/s
10bit 80MS/s 10bit 54MS/s

10bit 110MS/s 10bit 150MS/s

10bit 200MS/s 16bit 96KS/s

12bit 300KS/s


12bit 1MS/s


12bit 110MS/s