Embedded Array ASIC

Datasheets

• PDF CE81 Series - 0.18µm [122Kb]
• PDF CE77 Series - 0.25µm [160Kb]

Combining the advantages of Standard Cell and Gate Array ASICs, Fujitsu's Embedded Array product can offer a very interesting solution for ASIC designs of medium to high complexity, requiring large amounts of on-chip SRAM or analogue contents.

Embedded Array ASICs are - like Gate Array ASICs - based on the concept of a GATE formed by two N-channel plus two P-channel transistors. The digital logic function is realised by connecting these gates using metal or poly interconnect. This way, only a few masks are required to form e.g. NAND or NOR gates. More complex digital functions are composed by using multiple Gates.

Memory blocks are formed by using smaller transistors, custom logic blocks can be embedded into the design. Also PLL or ADC/DAC integration is possible. The digital area of the device is filled with a sea-of-gate structure of gates. This way the efficiency of RAMs is as high as in a Standard cell design, while keeping flexibility on the logic implementation. Hence silicon efficiency is higher than in gate arrays, but not as good as in standard cells. The same is true for power and speed requirements. Nevertheless Embedded Array ASIC outperforms FPGAs, both in terms of power efficiency and higher operating speeds, not to speak of part prices.

Another advantage of Embedded Array ASICs is the reduced turn-around-time from sign-off to sample delivery. This is possible because the mask generation and wafer level processing can be started as soon as the RAM and embedded cell configurations and locations are fixed, even if the digital logic design and layout is still at final design stage.

Fujitsu currently offers several Embedded Array technologies:

• 0.35 µm CE66
• 0.25 µm CE71/CE77
• 0.18 µm CE81/EA82