System LSI Timing Driven Layout Flow

• Restriction on chip level can be altered for each level of design.
• Top-down timing takes into consideration the timing restrictions at each design level.
• Full-fledged implementation of the forward-annotation concept can eliminate post-layout timing issues.
• By eliminating post-layout returns, design TAT can be substantially reduced.
• An ideal top-down stage design is possible by optimizing the timing budget for the lower-stage modules.
• Fujitsu offers an integrated layout environment, ranging from automatic generation of variable frames through to final verification.
• Features contributing to the timing driven layout flow include:
  
  • Power-supply wiring-planning function for the floor-planning stage
  • Timing-driven design methodology
  • Fully automatic clock-generation system
  • Static or dynamic current analysis and verification system for precise verification of current density, voltage drop and cross-talk effects
  • Layout system that takes signal integrity into account
  • Automatic correction for post-layout timing errors
  • Optimal scan-chain generation based on layout information

Hierarchical vs. Flat

• ASIC: Methodology - Hierarchical vs Flat Design less than 2M gates
  
  • Floor planning / timing driven layout
  • Timing optimization/ECO
• Design Larger than 2M gates
  
  • Design partition/hierarchical methodology required
  • Red blocks separately implemented as hard macros
  • Top level Inter Block routing and timing optimization

Floor plan & Synthesis Link

• Because the technology implements logic design based on floor plan data from the initial stage, post-layout timing errors are reduced, which greatly decreases the redesign processes required for timing error correction.

I/O Frame Generation

• Package Library Generation Function
  Product-specific package libraries can be generated by inputting data about the specific product's pin attributes (such as analog and APLL) as well as its power-supply characteristics.
• Frame Library Generation Function
  The chip frame libraries, which are necessary for the layout, can be generated automatically by inputting logic connection and pin assignment information.

Automatic Clock Tree Synthesis

• Automatic positioning of clock buffer takes into account implementation delays and skew.
• Wiring delay estimates and skew computation by RC delay can be implemented with the outlined wiring base.
• Tree generation takes into account the internal delay of macro cell.

3D RC Extraction

Accurate RC sampling and wiring delay computation are possible, using ultra-precision three-dimensional capacitance models that are based on Field Solver analysis results.

Current Analysis

Analysis Results (Current Distribution)

• Power consumption is estimated in line with the design stage.
• Both static and dynamic analyses are possible.
• The power supply grid detects the hot spot and an inspection determines whether the voltage drop and current density are within the limits. Based on this inspection, the optimal width of the power supply and wiring for the chip size can be determined.
• The range for the power source can be determined at the floor planning stage. As a result, chip size and power consumption can be estimated from the initial design stage.

Signal Integrity

• Signal integrity is analyzed, based on the results of the Field Solver analysis.
• Cross-talk between parallel wiring is checked.
• Based on the results, an Xtalk delay penalty can be reflected in the static timing analysis.
• Because of the peak current analysis, the voltage drop and switching noise are verified accurately.
• An S1 aware routing algorithm is used to prevent signal integrity problems.

Deep-Submicron High-Precision Delay Model

• Nonlinear delay model considering input waveform skew and output load
• Delay parameter model with PTV (Process, Temperature, Voltage)