Macro Embedded Cell Array
Macro embedded cell arrays are LSIs that incorporate optimum-sized macros from the transistor level (similar to that of standard cells) on the gate arrays. Their manufacture begins after floor planning (macro placement, etc), so the post-design development period is the same as that for gate arrays, resulting in higher-performance LSIs than gate arrays.
| Specifications | Documentation | |
|---|---|---|
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CE81 series – 0.18 micron technology | PDF PDF |
| CE77 series – 0.25 micron technology | PDF PDF | |
| CE71 series – 0.25 micron technology | PDF PDF | |
| CE66 series – 0.35 micron technology | PDF PDF | |
| CE61 series – 0.35 micron technology | PDF PDF | |
| CE46 series – 0.65 micron technology | PDF PDF |
