FUJITSU

IP Macros

IP Macros detail
Category Function 0.35µm 0.25µm 0.18µm 0.11µm
CPU Core FR Core
FRV Core
ARM7TDMI
ARM926EJ-S / ARM946E-S
*
-
-
-
-
-
*
-
*
*
*
*
Developing
Planning
-
*
DSP Core Hiperion2 (16bit)
Hiperion32(32bit)
-
-
-
*
*
*
Planning
-
Memory FRAM (2T2C)
           (1T1C)
*
Developing
-
-
-
Developing
-
-
DAC 8Bit /50Msps
10Bit /30Msps
10Bit /50Msps
*(3.3V)
*(3.3V)
-
*(2.5V)
*(2.5V)
-
*(3.3V)
-
*(3.3V)
Planning
-
Planning
ADC 8Bit /50Msps
10Bit /30Msps
10Bit /50Msps
*(3.3V)
*(3.3V)
-
*(2.5V)
*(2.5V)
-
*(3.3V)
-
*(3.3V)
Planning
-
Planning
Media Access JPEG CODEC
MPEG4 CODEC (VGA)
NTSC/PAL Encoder
VoIP Codec (ARC + Matrix DSP)
*
-
*
-
*
-
*
*
*
Developing
*
*
*
Developing
*
*
Standard Bus Controller USB1.1 Host * * * *
Function * * * *
USB2.0 Function - Link - - * *
Function - Phy - - * *
PCI Ver 2.3 * * * Developing
IEEE1394 S100 AVp - * - -
S400 AVp - - * Planning
OHCI - * * Planning
IrDA Ver 1.0, 1.1, 1.2 * * * *
Memory Stick Host * * * *
Serial I/F 8251 * * * *
UART * * * *
Parallel I/F 8255 * * * *
I 2 C I/F Master/Target * * * *
E-IDE Host * * * *
PCMCIA Host * * * *
HDLC * * * *
Networking and Communication GMAC 10M/ 100M/ 1G
155/ 622Mbps CDR
622M/ 1.25G/2.5Gbps CDR
6.4Gbps CDR
10Gbps CDR
3.125Gbps XAUI
SFI-4
SFI-5 ( Source Sync), SPI-5
SPI4-II
-
-
-
-
-
-
-
-
-
*
-
-
-
-
-
-
-
-
Developing
*
*
-
-
*
*
-
*
Developing
*
*
Developing
*
*
*
*
*

Note : The above list is not an exhaustive one, please contact Fujitsu for more product updates.