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Performance Boards

0.5mm pitch through hole PCB for fine pitch CSP burn-in test applications in mass production.

  • SMT type LSI socket can be applied with Via in PAD structure.
  • Electroless gold plating provide durability for repeated assembly and repair operation.

Wiring specification at 0.5mm pitch pad distribution area

Via pitch : 0.5mm [mm]
FIN diameter φ0.100
Drill diameter φ0.200
Surface Land diameter φ0.420
Line width Layout disabled
Pad-Line space Layout disabled
Inner layer Land diameter φ0.450
Line width 0.080
Pad-Line space Layout disabled
Hole-Line space 0.085
relief diameter 口0.420
Solder mask relief diameter
of Via in Pad
Area
Total thickness
≦4.8
  1. We recommend copper plating or electroless gold plating as the surface finishing.
  2. Please feel free to contact us for the specification other than the above.

Surface

Except the most outsided pads in the 0.5mm pitch pad array, the trace can not be connected to pads on the surface layer.

Except the most outsided pads in the 0.5mm pitch pad array, the trace can not be connected to pads on the surface layer.

Inner layer (signaling layer)

When trace is placed between 0.5mm pitch vias, the pad can be placed only the point where the trace connected to via.

When trace is placed between 0.5mm pitch vias, the pad can be placed only the point where the trace connected to via.


Applications

  • Burn-in test device
  • Semiconductor test device