MB86064

Dual 14-bit 1GSa/s Digital to Analog Converter

Product Data

• PDF MB86064 Product Flyer [123 KB]
• PDF MB86064 Development Kit Flyer - Version 2 [147 KB]
• PDF Product Datasheet [1.05 MB]
• PDF Application Notes [39.7 KB]

The Fujitsu MB86064 is a Dual 14-bit 1GSa/s digital to analog converter (DAC), delivering exceptional dynamic performance. Each high performance DAC core is capable of generating multi-carrier, multi-standard communication transmit signals, suitable for 2, 2.5 and 3G systems. DAC data is input via two high-speed LVDS ports. These operate in a pseudo double data rate (DDR) mode, with data latched on both rising and falling edges. Alternatively, the device can be configured as a multiplexed dual port single DAC. To simplify system integration the DAC operates from a clock running at half the DAC conversion rate. Analog performance at high frequencies is enhanced by novel current switch and switch driver designs which provide constant data-independent switching delay, reducing jitter and distortion.

Features

• Dual 14-bit, 1GSa/s Digital to Analog conversion
• Exceptional dynamic performance
  
  • 74dBc ACLR for 4-carrier UMTS @ 276MHz direct-IF
• 100MHz generated bandwidth capability
  
  • supports UMTS plus digital pre-distortion bandwidth
• Proprietary performance enhancement features
• LVDS data & clock interface
• Register selectable on-chip LVDS termination resistors
• Fujitsu 4-wire serial control interface (1.8V LVCMOS)
• Two 16k point programmable on-chip waveform memories
• 590mW per DAC power dissipation at 800MSa/s
• 0.18µm CMOS technology with Triple Well
• Performance enhanced EFBGA package
• Industrial temperature range (-40°C to +85°C)

An example of implementing the high speed LVDS data interface using a Stratix™ FPGA has been documented by Altera. This reference design comprises two 14-bit parallel buses, each running at up to 800 million samples per second (MSPS). A key feature is the combination of the Stratix enhanced phase-locked loop (PLL) with the MB86064 loop-clock facility to maintain optimum clock-to-data timing. Click the link below to visit the Altera web site and find out more about this reference design.

Altera and Stratix are trademarks of Altera Corporation

PDF High-Speed Data Interface for Stratix Devices & Fujitsu MB86064 DACs