DESCRIPTION

The MB90580/85 series is a member of 16-bit proprietary microcontroller F²MC-16LX family(F²MC stands for FUJITSU Flexible Microcontroller) designed to be combined with an ASIC (Application Specific IC) core. The MB90580/585 series is a high-performance general-purpose 16-bit microcontroller for controlling car audio electronic appliance. The instruction set of F²MC-16L CPU core inherits AT architecture of F²MC-8 family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data (32-bit). The MB90580/85 series has peripheral resources of a IE bus controller, UARTs, a 8/10-bit A/D converter, a 8-bit D/A converter, an I/O extended serial interace, a 8/16-bit PPG timer, 16-bit re-load timers, 16-bit PWC timer, a 16-bit I/O timer (a 16-bit free-run timer), a 18-bit timerbase counter/watch-dog timer, an output compare (OCU), an input capture (ICU), DTP/external interrupt circuit, Embedded peripheral resources performs data transmission with an intelligent I/O service function without the intervention of the CPU, enabling real-time control in various applications.

FEATURES

• Clock
  
  • the MB90585 series is the same as MB90580 series but without the IE Bus
  • Embedded PLL Clock Multiplication Circuit
  • Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz).
  • Minimum instruction execution time of 83.3 ns (at oscillation of 4 MHz, three times the PLL clock, operation at Vcc V_cc of 5.0 V)
• CPU addressing space of 16 Mbytes
  
  • Internal addressing of 24-bit
  • External accessing can be performed by selecting 8/16-bit bus width (external bus mode)
• Instruction set optimized for controller applications
  
  • Rich data types (bit, byte, word, long word)
  • Rich addressing mode (23 types)
  • High code efficiency
  • Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C) and multi-task operations
  
  • Adoption of system stack pointer
  • Enhanced pointer indirect instructions
  • Barrel shift instructions
• Enhanced execution speed: 4-byte instruction queue
• Enhanced interrupt function: 8 levels, 32 factors
• Automatic data transmission function independent of CPU operation: Extended intelligent I/O service function (EI²OS)
• Low-power consumption (stand-by) mode
  
  • Sleep mode (mode in which CPU operating clock is stopped)
  • Timebase timer mode (mode in which other than oscillation and timebase timer are stopped)
  • Stop mode (mode in which oscillation is stopped)
  • CPU intermittent operation mode
  • Hardware stand-by mode
• Process: CMOS technology
• I/O port: Maximum of 77 ports
• IE Bus: 1 channel
  
  • Small scale two-line serial bus interface for automotive and general industrial application
  • Maximium transfer rate is 27 Kbps
• Timers
  
  • 18-bit Timebase counter : 1 channel
  • Watch-dog timer : 1 channel
  • 15-bit Watch timer : 1 channel
  • 8/16-bit PPG timer: 8-bit x 2 channels or 16-bit x 1 channel
  • 16-bit re-load timer: 3 channels
  • 16-bit PWC timer (with noise filter) : 1 channel
  • 16-bit I/O timer (16-bit free-run timer): 1 channel
• Input capture (ICU) : 4 channels: Generates an interrupt request by latching a 16-bit free-run timer counter value upon detection of an edge input to the pin.
• Output compare (OCU) : 2 channels: Generates an interrupt request and reverse the output level upon detection of a match between the 16-bit free-run timer counter value and the compare setting value.
• UART : 5 channels
  
  • With full-duplex double buffer (8-bit length)
  • Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively used.
• DTP/external interrupt circuit : 8 channels: A module for starting extended intelligent I/O service (EI²OS) and generating an external interrupt triggered by an external input.
• Delayed interrupt generation module: Generates an interrupt request for switching tasks.
• Clock monitor function: Output the clock to I/O port (Dividing the machine clock by 2 to 28
• ROM correction module: Replace the internal ROM code by small external circuit
• ROM mirroring module: Used to increase the coding efficiency
• 10-bit A/D converter : 8 channels
  
  • 10-bit resolution can be selectively used.
  • Starting by an external trigger input.
• 8-bit D/A converter : 2 independent channels
  
  • 8-bit resolution.
  • -2R typet.

DOCUMENTATION

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PDF Datasheet for MB90580A,C V4-00 (110 pages, 1792 KB)

PDF Hardware Manual V2-00 (566 pages, 15663 KB)

PDF PF package 0.65mm QFP (1 page, 109 KB)