DESCRIPTION

The FUJITSU FR family of single-chip microcontrollers using a 32-bit high-performance RISC CPU, with a variety of built-in I/O resources and bus control mechanisms for built-in control applications requiring high-capability, high speed CPU processing. The Fr family is most suitable for embedded applications, for example, TV and PDP control that require a high level of CPU processing performance. The MB91319 is a FR60 series product based on the FR30/40 series CPU with enhanced bus access for higher speed operation.

FEATURES

• FR-CPU
  
  • 32-bit RISC, load/store architecture, 5-stage pipeline
  • Operating frequency 40MHz [with PLL: base frequency 10MHz]
  • 16-bit fixed length instructions (basic instructions), 1 instruction per cycle
  • Instructions for built-in applications: memory-to-memory transfer, bit processing, barrel shift etc.
  • Instructions adapted for high-level languages: function input/output instructions, register contents multi-load/ store instructions
  • Easier assembler notation: register interlock function
  • Built-in multiplier/instruction level support. Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles
  • Interrupt (PC, PS removal): 6 cycles, 16 priority levels
  • Harvard architecture for simultaneous execution of program access and data access
  • CPU hold 4-word queue allows advanced instruction fetch function
  • 4 GB expanded memory space enables linear access
  • Instruction compatible with FR family
• Bus interface
  
  • This bus interface is used for USB and OSDC macro connections. Operating frequency: Max. 20 MHz
  • 8- or 16-bit data output
  • Automatic wait cycle generator that can be programmed for each area and can insert waits because CS2 and CS3 are reserved for USB Function and OSDC respectively.
  • Built-in 64KB/48KB RAM to use as data RAM and instruction RAM
• DMA Controller
  
  • 5 channels
  • 3 transfer sources
  • Addressing mode with 32-bit full address specifications.
  • Supports demand, burst, step and block transfers
• Reload Timer
  
  • 16-bit timer; 3 channels
  • Internal clock that can be selected from frequency divided by 2, 8, and 32
• UART
  
  • Full duplex double buffer
  • 5 channels
  • Either asynchronous or CLK synchronous communication
  • Built-in timer
  • External clock can be used as the transfer clock
  • Error detection functions available
• I2C Interface
  
  • 4 channel I2C
  • Supports standard mode (100Kbps) and high-speed mode (400kbps).
  • Clock synchronization function
• USB Host Function
  
  • USB 1.0 support
  • 8KB RAM for storing parameters.
• OSDC Function
  
  • High-definition OSDC:
    
    • A font in 24x32 dots can be displayed up to 80 x 32
    • Two layered display of Main/CC
    • § 4096 characters at the maximum (including 16 characters for font ROM)
  • Analog RGB I/F: Max 50MHz
  • Digital RGB I/F: Max 90MHz
• Multifunction Timer
  
  • Low-pass filter that removes noise that is below the frequency of the set clock
  • Event count for signals from pin inputs.
  • Interval timer using seven types of clocks and external input clocks.
• A/D converter
  
  • 10-bit resolution,10-channel
  • Sequential comparator type, conversion time approx. 10µs
  • Conversion modes: single conversion mode, continuous conversion mode
• Other interval timers
  
  • 16-bit timer with 3 channels (U-timer)
  • Watchdog timer
• I/O port
  
  • Maximum 72 ports
• Other Features
  
  • Built-in oscillator circuit for clock source, PLL multiplier selection enabled
  • INIT reset pin
  • Also included: watchdog timer reset, software reset
  • Power-saving modes: stop mode, sleep mode supported
  • Gear functions
  • Built-in time base timer
  • CMOS technology: 0.25 µm
  • Supply voltage: Two sources of 3.3 V ± 0.3 V and 2.5 V ± 0.15V
• Package
  
  • LQFP-176, 0.5mm pitch, and 24mmx240mm

DOCUMENTATION

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PDF Data Sheet V1-00 (66 pages, 797 KB)

PDF MB91319R Data Sheet V1.00 (71 pages, 576 KB)

PDF Hardware Manual V2-00 (766 pages, 4391 KB)