DESCRIPTION

The FR30 family is the name given to the FR architecture devices implemented in Fujitsu's 0.35µm CMOS technology. The first devices available in the FR30 family are the MB91101 and MB91106, which are in 100 pin QFP or SQFP packages. These are essentially the same devices except that the MB91106 contains 127KB mask ROM, whilst the MB91101 is a ROMless device but containing 1KB of 2 way set associative, Instruction Cache.

The MB91101 can operate from a single 5V supply, using an on-chip regulator to generate the 3.3V core voltage internally, or from only 3.3V, like the MB91106. From a 12.5MHz clock it is possible via the PLL to run the CPU at 12.5, 25 or 50MHz. Therefore the minimum instruction execution time is 20ns.

Gear functions enable both CPU and peripherals to be independently run at lower speeds under software control. Stop and sleep modes and watchdog function are also available. The Cache or ROM is supplemented by 2KB of on chip RAM. The external bus controller runs at up to 25MHz, supports up to 25 address bits, can work with 8 or 16 bit data bus by each of the 6 programmable chip selects and although normally big endian, can work in little endian style for one of the chip selects.

The associated DRAM controller supports 2 banks of fast page mode memories by 2 CAS/1WE or 1CAS/2WE. Any unused pins in the bus interface can be implemented as port I/O. The DMA controller has 8 channels. The many on-chip peripherals of the MB91100 devices demonstrate the remarkable mix of processing performance coupled with true embedded control features that the FR represents.

The external interrupt controller supports 4 channels plus NMI. The 4 channel, 10 bit A/D converter can convert in 5.6 µs. There are three 16 bit reload timers and four 16 bit PWM timers. The three UARTs can support both asynchronous and synchronous transfers. Many pins are multiplexed with port I/O, which can be used if the other function is not required..