DESCRIPTION

The MB90570/A series is a general-purpose 16-bit microcontroller developed and designed by Fujitsu for process control applications in consumer products that require high-speed real time processing. It contains an I²C(Purchase of Fujitsu I²C components conveys a license under the Philips I²C Patent Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips) bus interface that allows inter-equipment communication to be implemented readily. This product is well adapted to car audio equipment, VTR systems, and other equipment and systems. The instruction set of F²MC-16LX CPU core inherits AT architecture of F²MC(F²MC stands for FUJITSU Flexible Microcontroller) family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data. The MB90570/A series has peripheral resources of an 8/10-bit A/D converter, an 8-bit D/A converter, UART (SCI), an extended I/O serial interface, an 8/16-bit up/down counter/timer, an 8/16-bit PPG timer, I/O timer (a 16-bit free run timer, an input capture (ICU), an output compare (OCU).

FEATURES

• Clock
  
  • Embedded PLL clock multiplication circuit
  • Operating clock (PLL clock) can be selected from 1/2 to 4x oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz).
  • Minimum instruction execution time : 62.5 ns (at oscillation of 4 MHz, 4x PLL clock, operation at V_CC of 5.0 V)
• Maximum memory space: 16 Mbytes
• Instruction set optimized for controller applications
  
  • Rich data types (bit, byte, word, long word)
  • Rich addressing mode (23 types)
  • Enhanced signed multiplication/division instruction and RETI instruction functions
  • Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C) and multi-task operations
  
  • Adoption of system stack pointer
  • Enhanced pointer indirect instructions
  • Barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed: 4-byte instruction queue
• Enhanced interrupt function: 8 levels, 34 factors
• Automatic data transmission function independent of CPU operation: Extended intelligent I/O service function (EI²OS): Up to 16 channels
• Embedded ROM size and types
  
  • Mask ROM: 128 Kbytes/256 Kbytes
  • Flash ROM: 256 Kbytes
• Embedded RAM size:
  
  • 6 Kbytes/10 Kbytes (mask ROM)
  • 10 Kbytes (flash memory)
  • 10 Kbytes (evaluation device)
• Low-power consumption (standby) mode
  
  • Sleep mode (mode in which CPU operating clock is stopped)
  • Stop mode (mode in which oscillation is stopped)
  • CPU intermittent operation mode
  • Hardware standby mode
• Process: CMOS technology
• I/O port
  
  • General-purpose I/O ports (CMOS): 63 ports
  • General-purpose I/O ports (with pull-up resistors): 24 ports
  • General-purpose I/O ports (open-drain): 10 ports
  • Total: 97 ports
• Timer
  
  • Timebase timer/watchdog timer: 1 channel
  • 8/16-bit PPG timer: 8-bit x 2 channels or 16-bit x 1 channel
• 8/16-bit up/down counter/timer: 1 channel (8-bit x 2 channels)
• 16-bit I/O timer
  
  • 16-bit free run timer: 1 channel
  • Input capture (ICU): Generates an interrupt request by latching a 16-bit free run timer counter value upon detection of an edge input to the pin.
  • Output compare (OCU): Generates an interrupt request and reverse the output level upon detection of a match between the 16-bit free run timer counter value and the compare setting value.
• Extended I/O serial interface: 3 channels
• I²C interface (1 channel): Serial I/O port for supporting Inter IC BUS
• UART0 (SCI), UART1 (SCI)
  
  • With full-duplex double buffer
  • Clock asynchronized or clock synchronized transmission can be selectively used.
• DTP/external interrupt circuit (8 channels): A module for starting extended intelligent I/O service (EI²OS) and generating an external interrupt triggered by an external input.
• Delayed interrupt generation module: Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels)
  
  • 8/10-bit resolution
  • Starting by an external trigger input.
  • Conversion time: 26.3µs
• 8-bit D/A converter (based on the R-2R system)
  
  • 8-bit resolution: 2 channels (independent)
  • Setup time: 12.5µs
• Clock timer: 1 channel
• Chip select output (8 channels): An active level can be set.
• Clock output function

DOCUMENTATION

Note: The use of Adobe® Acrobat Reader is recommended to have all download and browsing features available for pdf files.

PDF Datasheet V8-00 (120 pages, 1755 KB)

PDF Hardware Manual V7-00 (527 pages, 16245 KB)

PDF Hardware Manual Correction X1-04 (12 pages, 210 KB)

PDF Hardware Manual Errata V7-02 (3 pages, 90 KB)

PDF PFF package 0.4mm LQFP (1 page, 74 KB)

PDF PFV package 0.5mm QFP (1 page, 119 KB)

PDF CR package Xmm PGA (1 page, 47 KB)