DESCRIPTION

The MB90520 series is a general-purpose 16-bit microcontroller developed and designed by Fujitsu for process control applications in consumer products that require high-speed real-time processing. The instruction set of F²MC-16LX CPU core inherits AT architecture of F²MC(F²MC stands for FUJITSU Flexible Microcontroller) family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data. The MB90520 series has peripheral resources of 8/10-bit A/D converter, a 8-bit D/A converter, UART (SCI), extended I/O serial interfaces 0 and 1, 8/16-bit up/down counter/timers 0 and 1, 8/16-bit PPG timers 0 and 1, I/O timer (16-bit free-run timers 1 and 2, input captures 0 and 1 (ICU), output compares 0 and 1 (OCU), LCD controller/driver..

FEATURES

• Clock
  
  • Embedded PLL clock multiplication circuit
  • Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 3 MHz to 16 MHz).
  • The system can be operated by an oscillation sub-clock (rated at 32.768 kHz).
  • Minimum instruction execution time: 62.5 ns (at oscillation of 4 MHz, four times the PLL clock, operation at Vcc of 5.0 V)
• Maximum memory space: 16 Mbytes
• Instruction set optimized for controller applications
  
  • Rich data types (bit, byte, word, long word)
  • Rich addressing mode (23 types)
  • Enhanced signed multiplication/division instruction and RETI instruction functions
  • Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C) and multi-task operations
  
  • Adoption of system stack pointer
  • Enhanced pointer indirect instructions
  • Barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed: 4-byte instruction queue
• Enhanced interrupt function: 8 levels, 34 factors
• Automatic data transmission function independent of CPU operation: Extended intelligent I/O service function (EI²OS): Up to 16 channels
• Embedded ROM size and types
  
  • Mask ROM: 64 kbytes/128 kbytes
  • Flash ROM: 256 kbytes Embedded RAM size: 4 kbytes/10 kbytes (mass-produced products)
    
    • 4 kbytes (flash memory)
    • 6 kbytes (evaluation chip
• Low-power consumption (stand-by) mode
  
  • Sleep mode (mode in which CPU operating clock is stopped)
  • Stop mode (mode in which oscillation is stopped)
  • CPU intermittent operation mode
  • Hardware stand-by mode
  • Clock mode (mode in which other than sub-oscillation and timebase timer are stopped)
• Process: CMOS technology
• I/O port
  
  • General-purpose I/O ports (CMOS): 53 ports
  • General-purpose I/O ports (via pull-up resistors): 24 ports
  • General-purpose I/O ports (open-drain): 8 ports
  • Total: 85 ports
• Timer
  
  • Timebase timer/watchdog timer: 1 channel
  • 8/16-bit PPG timers 0, 1: 8-bit x 2 channels or 16-bit x 1 channel
  • 16-bit re-load timers 0, 1: 2 channels
• 16-bit I/O timer
  
  • 16-bit free-run timers 1, 2: 2 channels
  • Input captures 0, 1 (ICU): Generates an interrupt request by latching a 16-bit free-run timer counter value upon detection of an edge input to the pin.
  • Output compares 0, 1 (OCU): Generates an interrupt request and reverse the output level upon detection of a match between the 16-bit free-run timer counter value and the compare setting value.
  • 8/16-bit up/down counter/timers 0, 1: 1 channel (8-bit x 2 channels)
• Extended I/O serial interfaces 0, 1: 1 channel
• UART (SCI)
  
  • With full-duplex double buffer
  • Clock asynchronized or clock synchronized transmission can be selectively used.
• DTP/external interrupt circuit (8 channels): A module for starting extended intelligent I/O service (EI²OS) and generating an external interrupt triggered by an external input.
• Wake-up interrupt: Receives external interrupt requests and generates an interrupt request upon an "L" level input.
• Delayed interrupt generation module: Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels)
  
  • 8/10-bit resolution can be selectively used.
  • Starting by an external trigger input.
  • Conversion time: 16.0µs or slower
• 8-bit D/A converter (based on the R-2R system)
  
  • 8-bit resolution: 2 channels (independent)
  • Setup time: 12.5µs
• Clock timer: 1 channel
• LCD controller/driver: A common driver and a segment driver that can directly drive the LCD (liquid crystal display) panel
• Clock output function
• Note: Do not set external bus mode for the MB90520 series because it cannot be operated in this mode.

DOCUMENTATION

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PDF Datasheet V4-00 (106 pages, 1.542 KB)

PDF Datasheet for A/B Series V3-00 (99 pages, 980 KB)

PDF MB90520A Series Hardware Manual V2-00 (806 pages, 4590 MB)

PDF Hardware Manual Corrections X1-04 (13 pages, 421 KB)

PDF PFF package 0.4mm LQFP (1 page, 74 KB)

PDF PFV package 0.5mm QFP (1 page, 119 KB)

PDF CR package Xmm PGA (1 page, 47 K)