ASIC

Methodology - Signal Integrity

• Signal integrity is analyzed, based on the results of the Field Solver analysis.
• Cross-talk between parallel wiring is checked.
• Based on the results, an Xtalk delay penalty can be reflected in the static timing analysis.
• Because of the peak current analysis, the voltage drop and switching noise are verified accurately.
• An S1 aware routing algorithm is used to prevent signal integrity problems.

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Related Links

• System LSI Design Flow
  
  • HW/SW Co-Simulation
  • Emulation
  • Total Development TAT
  • Low Power Design
  • Logic Verification
  • Static Timing Analyzer
  • Formal Verification
• System LSI Test Interface Flow
  
  • Test CAD Flow
  • Test Synthesis
• System LSI Timing Driven Layout Flow
  
  • Hierarchical vs. Flat
  • Floorplan & Synthesis Link
  • I/O Frame Generation
  • Automatic Clock Tree Synthesis
  • 3D RC Extraction
  • Current Analysis
  • Signal Integrity
  • Deep-Submicron High-Precision Delay Model