ASIC

Methodology - I/O Frame Generation

• Package Library Generation Function
  Product-specific package libraries can be generated by inputting data about the specific product's pin attributes (such as analog and APLL) as well as its power-supply characteristics.
• Frame Library Generation Function
  The chip frame libraries, which are necessary for the layout, can be generated automatically by inputting logic connection and pin assignment information.

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Related Links

• System LSI Design Flow
  
  • HW/SW Co-Simulation
  • Emulation
  • Total Development TAT
  • Low Power Design
  • Logic Verification
  • Static Timing Analyzer
  • Formal Verification
• System LSI Test Interface Flow
  
  • Test CAD Flow
  • Test Synthesis
• System LSI Timing Driven Layout Flow
  
  • Hierarchical vs. Flat
  • Floorplan & Synthesis Link
  • I/O Frame Generation
  • Automatic Clock Tree Synthesis
  • 3D RC Extraction
  • Current Analysis
  • Signal Integrity
  • Deep-Submicron High-Precision Delay Model