ASIC

Methodology - Hierarchical vs Flat

• Design less than 2M gates
  
  • Floor planning/timing driven layout
  • Timing optimization/ECO
• Design Larger than 2M gates
  
  • Design partition/hierarchical methodology required
  • RED blocks separately implemented as hard macros
  • Top level Inter Block routing and timing optimization

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Related Links

• System LSI Design Flow
  
  • HW/SW Co-Simulation
  • Emulation
  • Total Development TAT
  • Low Power Design
  • Logic Verification
  • Static Timing Analyzer
  • Formal Verification
• System LSI Test Interface Flow
  
  • Test CAD Flow
  • Test Synthesis
• System LSI Timing Driven Layout Flow
  
  • Hierarchical vs. Flat
  • Floorplan & Synthesis Link
  • I/O Frame Generation
  • Automatic Clock Tree Synthesis
  • 3D RC Extraction
  • Current Analysis
  • Signal Integrity
  • Deep-Submicron High-Precision Delay Model