ASIC

Methodology - Current Analysis

Analysis Results (Current Distribution)

• Power consumption is estimated in line with the design stage.
• Both static and dynamic analyses are possible.
• The power supply grid detects the hot spot and an inspection determines whether the voltage drop and current density are within the limits. Based on this inspection, the optimal width of the power supply and wiring for the chip size can be determined.
• The range for the power source can be determined at the floor planning stage. As a result, chip size and power consumption can be estimated from the initial design stage.

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Related Links

• System LSI Design Flow
  
  • HW/SW Co-Simulation
  • Emulation
  • Total Development TAT
  • Low Power Design
  • Logic Verification
  • Static Timing Analyzer
  • Formal Verification
• System LSI Test Interface Flow
  
  • Test CAD Flow
  • Test Synthesis
• System LSI Timing Driven Layout Flow
  
  • Hierarchical vs. Flat
  • Floorplan & Synthesis Link
  • I/O Frame Generation
  • Automatic Clock Tree Synthesis
  • 3D RC Extraction
  • Current Analysis
  • Signal Integrity
  • Deep-Submicron High-Precision Delay Model