ASIC

Methodology

Fujitsu's design methodology ensures first-silicon success by integrating proprietary point tools with the most popular industry-standard CAD tools.

Fujitsu's clock-driven design methodology offers low power and low skew. It identifies the best-suited clock distribution strategy for a given design and predicts performance in advance. Fujitsu supports co-simulation, emulation, and high-level floorplanning to ease estimation of the design's power, timing and size. This enables the designer to make effective architectural-level decisions to achieve optimal design solutions.

Fujitsu's design methodology supports cycle-based simulators and formal verification, as well as static timing analysis and the more conventional VHDL and Verilog simulators. Fujitsu's design-for-test strategy includes boundary scan (JTAG), full and partial scans, as well as a built-in self-test for memory.

• System LSI Design Flow
  
  • HW/SW Co-Simulation
  • Emulation
  • Total Development TAT
  • Low Power Design
  • Logic Verification
  • Static Timing Analyzer
  • Formal Verification
• System LSI Test Interface Flow
  
  • Test CAD Flow
  • Test Synthesis
• System LSI Timing Driven Layout Flow
  
  • Hierarchical vs. Flat
  • Floorplan & Synthesis Link
  • I/O Frame Generation
  • Automatic Clock Tree Synthesis
  • 3D RC Extraction
  • Current Analysis
  • Signal Integrity
  • Deep-Submicron High-Precision Delay Model