ASIC

Design Resources

Fujitsu’s innovative design methodology incorporates the best-in-class third-party or in-house EDA tools. The company’s hierarchical physical-design flow provides a scalable solution for implementation of designs far in excess of 10 million gates. Fujitsu’s methodology resolves issues associated with nanometer design upfront, through extensive use of physical-synthesis technologies, multi-Vth library support, power-supply integrity analysis, Xtalk noise avoidance, analysis and fixing. These capabilities, combined with a robust verification environment enable Fujitsu to achieve rapid closure in the timing, signal integrity and power arenas, shortening the time to silicon.

Methodology
Fujitsu's design methodology ensures first-silicon success by integrating proprietary point tools with the most popular industry-standard CAD tools.

• System LSI Design Flow
  
  • HW/SW Co-Simulation
  • Emulation
  • Total Development TAT
  • Low Power Design
  • Logic Verification
  • Static Timing Analyzer
  • Formal Verification
• System LSI Test Interface Flow
  
  • Test CAD Flow
  • Test Synthesis
• System LSI Timing Driven Layout Flow
  
  • Hierarchical vs. Flat
  • Floorplan & Synthesis Link
  • I/O Frame Generation
  • Automatic Clock Tree Synthesis
  • 3D RC Extraction
  • Current Analysis
  • Signal Integrity
  • Deep-Submicron High-Precision Delay Model

Tools
Fujitsu's design environment utilizes industry-leading tools from the major EDA companies such as Synopsys, Cadence and Mentor Graphics. Internally developed tools supplement this environment at specific points, resulting in an integrated and efficient system. Multi-platform support is also provided for products such as Sun and HP workstations.

Design Services
Fujitsu's design services are integrated for optimum effectiveness. The services include:

• Library and tool support teams
• Methodology teams
• High-speed IO design and expertise
• Mixed signal design capability and team
• Vertical expertise and IP cores (system architects)
• RTL synthesis
• Design partitioning and floor planning
• Timing analysis
• Scan and test insertion
• Timing-driven place and route
• Timing closure
• Design sign off
• Test and product engineering
• Operations support