Fujitsu Microelectronics America, Inc.

Fujitsu Continues ASIC Leadership with 90-nanometer CS101 CMOS Standard Cell Series for Mobile, Telecommunications and Networking Markets

Thirteen new designs underway using leading-edge 90nm process technology

Sunnyvale, CA, September 22, 2004 — Fujitsu Microelectronics America, Inc. (FMA) and Fujitsu Limited are now developing a total of 13 new high-performance ASICs for a variety of networking, CPU and mobile communications applications using 90-nanometer process technology. Three of the new 90nm ASICs are in production. The new, highly complex designs incorporate between 6 million and more than 25 million logic gates and 20 to 30Mbits of SRAM, in addition to high-speed serial interfaces operating at up to 6.4Gbps.

Fujitsu has been accepting advanced standard cell ASIC designs using the company’s 90nm technology since mid-2003, and continues to lead the industry in the development of high-performance, high-density designs. The state-of-the-art 90nm CS101 CMOS standard cell ASIC series serves applications that require very high integration with a small form factor, low power consumption and low leakage current. The CS101 series features a full set of application specific and commercial IP, including ARM and DSP cores, PCI Express, analog-to-digital (ADC) and digital-to-analog (DAC) converters and a variety of other high speed interfaces.

“Fujitsu has a long and successful history in leading-edge ASIC development and process technology, and today’s announcement continues and expands our leadership in high-performance ASIC design and production,” said Keith Horn, vice president of marketing for Fujitsu Microelectronics America. “Our 90nm CS101 ASIC technology is an excellent choice for networking, communications and mobile-device applications where low power and a small footprint must combine with maximum performance. We are working quickly on a significant number of new designs in all these sectors. With the new 300mm fab, Fujitsu can assure our customers that we have the capacity to address their volume requirements..”

Reduced Chip Size, High Gate Count, Available Library and Other Support
The new CS101 ASIC series provides a high level of functional integration using 10-layer fine pitch, copper wiring and low-k insulation material, along with a PAD-on-I/O structure with fine PAD-pitch technology that enables chip size reduction. The series enables designs with up to 91 million gates, almost twice the number available with Fujitsu’s 0.11-micron technology. Propagation delay is only 12 picoseconds at 1.2 volt and F/O=1.

The series is available with a complete library of high-speed and low-power libraries, including ultra-high-speed and low-leakage versions. Standard I/Os include LV-TTL, LVDS, SSTL, HSTL, and P-CML. Compiled memory macros include SRAMs and ROM. Supply voltages range from 0.80V to 1.30V for the core; and packaging options include QFP, FBGA, EBGA, PBGA, and FC-BGA. Design center support is available at FMA’s facilities in Sunnyvale and Dallas, and Fujitsu’s worldwide design service organizations deliver global support.

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About Fujitsu Microelectronics America

Fujitsu Microelectronics America, Inc. (FMA) leads the industry in innovation. FMA provides high-quality, reliable semiconductor products and services for the networking, communications, automotive, security and other markets throughout North and South America. For product information, visit the company web site at http://www.fma.fujitsu.com/ASIC

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