Fujitsu Microelectronics America, Inc.

Fujitsu Microelectronics America Releases System Packet Interface Level-4 I/O Macro for High-End Networking Applications

Newest in series of high-end I/Os for SoC ASICs joins SFI-4, SFI-5, transceiver macros

Sunnyvale, CA, April 14, 2003 — Fujitsu Microelectronics America, Inc. (FMA), an industry leader in advanced macros and IPs for high-end network development, today introduced its SPI-4 (System Packet Interface Level-4) I/O macro, providing point-to-point connectivity between physical layer and link layer devices in network designs.

The new SPI-4 macro is compliant with OIF SPI4-02.0, phase 2 standard, and supports bandwidths for OC-192, 10Gb/second Ethernet and Packet over SONET (PoS) applications, along with multiplexing/demux and bridging functions. It is fabricated in both Fujitsu’s advanced 0.11-micron and 0.18-micron CMOS process. The 0.11-micron version uses supply voltages of 1.2V and 2.5V while the 0.18-micron version uses supply voltages of 1.8V and 3.3V. This macro is available now and been applied in a variety of complex ASIC designs.

The new SPI-4 joins Fujitsu’s family of world-class, high-speed interface macros for optical long haul, metro area network and enterprise applications. This series includes XAUI-compliant 3.125Gbps transceivers, OC-48 compliant 2/4/8/16-channel 3.125Gbps transceivers, an OIF compliant 16-channel SFI-4 (SERDES Framer Interface-4) macro and the OIF compliant 16-channel SFI-5 macro. These macros are designed using Fujitsu’s advanced 0.11-micron and 0.18-micron process, with proven reliability and manufacturability. All are supported by high-performance ASIC libraries that include dense memory macros, along with a variety of state-of-the-art flip-chip packages. FMA provides full support for all the high-speed I/O macros, together with Verilog and design compiler models and library exchange format for floor planning.

“High-performance applications will be one of the strongest areas in the ASIC industry, and the companies that can meet the demands of these high-end opportunities will be well-positioned,᾿ said Jordan Selburn, principal analyst of application specific semiconductors and PLDs at iSuppli Corporation. “Standards compliance also will be essential to meet the needs of the segment,᾿ he added.

“Our new SPI-4 phase 2 macro in 0.11-micron adds yet another valuable component to our ‘best-of-breed’ high-speed I/O family,᾿ said Marwan Majid, senior product marketing manager at FMA. “We have developed this series specifically to enable our networking customers to design complex high-performance ASICs for their high-end systems and products. Our design engineering teams work closely with customer engineers to identify specific IP requirements and provide complete support, so customers can meet their time-to-market objectives with confidence.᾿

For a detailed data sheet on the new System Packet Interface Level-4 macro, visit
http://www.fma.fujitsu.com/pdf/spil4.pdf

2.5Gbps Transceiver Macro:
http://www.fma.fujitsu.com/pdf/25Gbps.pdf

3.125Gbps Parallel CDR Transceiver:
http://www.fma.fujitsu.com/pdf/xauicdr.pdf
http://www.fujitsumicro.com/pdf/3125cdr.pdf

3.125Gbps x4 Parallel Transceiver (XAUI):
http://www.fma.fujitsu.com/pdf/xaui4.pdf
http://www.fma.fujitsu.com/pdf/xaui.pdf

SERDES Framer Interface:
http://www.fujitsumicro.com/pdf/sfi5.pdf

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About Fujitsu Microelectronics America

Fujitsu Microelectronics America, Inc. (FMA) leads the industry in innovation. FMA provides high-quality, reliable semiconductor products and services for the networking, communications, automotive, security and other markets throughout North and South America. Fujitsu is the world’s second largest supplier of ASIC products and technology. For product information, visit the company web site at http://www.fma.fujitsu.com/ASIC

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