Publications

a) Formal Verification of RTL designs

• I. Ghosh, M. Prasad, M. Fujita, "High level verification techniques for system LSI designs," in International Symposium on Circuits and Systems, Kobe, Japan, May, 2005 (Tutorial).
• Mukul R. Prasad, Armin Biere and Aarti Gupta, "A Survey of Recent Advances in SAT-based Formal Verification," in International Journal on Software Tools for Technology Transfer (STTT), January 2005, Springer-Verlag.
• Indradeep Ghosh, Mukul R. Prasad, Rajarshi Mukherjee and Masahiro Fujita, "Current Practices and Future Directions in High-level Design Validation," in Proceedings of the Asia South Pacific Design Automation Conference (ASPDAC), Shanghai, China, January 2005, (Tutorial.)
• D. Sahoo, S. Iyer, J. Jain, C. Stangier, A. Narayan, D. Dill, E. A. Emerson, “A Partitioning Methodology for BDD-based Verification,” In Formal Method in Computer-Aided Design, 5th International Conference, Austin, USA, November 14-17, 2004. Also in Proceedings of the 13th IEEE/ACM International Workshop on Logic & Synthesis, pp. 192-199, Temecula, USA, June 2-4, 2004.
• Liang Zhang, Mukul R. Prasad and Michael S. Hsiao, "Incremental Deductive & Inductive Reasoning for SAT-based Bounded Model Checking," in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2004. Also, in Proceedings of the 13th IEEE/ACM International Workshop on Logic & Synthesis, June 2004.
• S. Iyer, D. Sahoo, C. Stangier, A. Narayan, J. Jain, “Improved Symbolic Verification using Partitioning Techniques,” In Proceedings of the 12th IFIP Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME), pp. 410-424, L'Aquila, Italy, October 21-24, 2003. Also in Proceedings of the 12th IEEE/ACM International Workshop on Logic & Synthesis, pp. 236-243, Laguna Beach, USA, May 28-30, 2003.
• Mukul R. Prasad, Michael S. Hsiao and Jawahar Jain, "Can SAT be used to Improve Sequential ATPG Methods ?", in Proceedings of 17th International Conference on VLSI Design and 3rd International Conference on Embedded Systems, Jan 2004. Also in proceedings of International Workshop on Logic and Synthesis (IWLS), New Orleans, June 2002.
• Indradeep Ghosh, Mukul Prasad, Rajarshi Mukherjee, and Masahiro Fujita, "High Level Design Validation: Current Practices and Future Directions," in 17th International Conference on VLSI Design and 3rd International Conference on Embedded Systems, Mumbai, India, Jan 2004,
• Kelvin Ng, Mukul R. Prasad, Rajarshi Mukherjee and Jawahar Jain, "Solving the Latch Mapping Problem in an Industrial Setting," in Proceedings of the 40th Design Automation Conference, June 2003.
• F. Fallah, P. Ashar, S. Devadas, "Functional Vector Generation for Sequential HDL Models under an Observability-Based Code Coverage Metric," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Dec. 2002.
• F. Fallah, Binary Time-Frame Expansion, International Conference on Computer Aided Design (ICCAD), San Jose, Nov. 2002. Also in proceedings of International Workshop on Logic and Synthesis (IWLS), New Orleans, June 2002.
• Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan, "Functional Verification of System on Chips-Practices, Issues and Challenges", ASP-DAC/VLSI Design 2002, 7-11 January 2002 (Tutorial).
• R. Murgai, A. Aziz, G. Swamy, and A. Narayan, "Design Validation Techniques," in VLSI Design, India, 1998 (Tutorial).
• R. Murgai, A. Aziz, G. Swamy, and A. Narayan, "Design Validation Techniques," the Design Automation Conference, 1998 (Tutorial).

b) Register Transfer ATPG & Validation

• L. Zhang. I. Ghosh and M. Hsiao, "Efficient sequential ATPG for functional RTL circuits," in Proc. International Test Conference, Charlotte, North Carolina, Sept. 2003.
• L. Zhang. I. Ghosh and M. Hsiao, "Automatic Design Validation Framework for HDL Descriptions via RTL ATPG," in Proc. Asian Test Symposium, Xian, China, Nov. 2003. Also in Tenth International Test Synthesis Workshop, Santa Barbara, California, May 2003.
• I. Ghosh, S. Ravi, "On automatic generation of RTL validation test benches using circuit testing techniques," in Proc. Great Lakes Symposium on VLSI, Washington D.C, April 2003.
• F. Fallah, K. Takayama, "A New Functional Test Program Generation Methodology," International Conference on Computer Design (ICCD), Texas, Sept. 2001. Also in International Workshop on Logic and Synthesis (IWLS), California, June 2001.
• S. Tasiran, F. Fallah, D. G. Chinnery, S. J. Weber, K. Keutzer, "A Functional Validation Technique: Biased Random Simulation Guided by Observability-Based Coverage," International Conference on Computer Design (ICCD), Texas, Sept. 2001.
• F. Fallah, S. Devadas, K. Keutzer, "OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Aug. 2001.
• F. Fallah, S. Devadas, K. Keutzer, "Functional Vector Generation for HDL Models Using Linear Programming and Boolean Satisfiability," IEEE Transactions on Computer-Aided Desiign of Integrated Circuits and Systems, Aug. 2001.
• S. Tasiran, F. Fallah, D. G. Chinnery, S. J. Weber, K. Keutzer, "Coverage-Directed Generation of Biased Random Inputs for Functional Validation of Sequential Circuits," International Workshop on Logic and Synthesis (IWLS), California, June 2001.
• F. Fallah, S. Devadas, "Functional Vector Generation from HDL Models for Observability-Based Code Coverage Metric," SCI2000/ISAS2000, Orlando, July 2000.
• I. Ghosh, M. Fujita "Automatic test pattern generation for functional RTL circuits using assignment decision diagrams," in IEEE Transactions on CAD, March 2001. Also in Proceedings of IEEE/ACM Design Automation Conference, Los Angeles, California, June 2000.

c) Design for verification Methodology

• Ghosh, K. Sekar and V. Boppana, "Design for verification at the register transfer level," in Proc. Asia and South Pacific Design Automation Conference,Bangalore, India, Jan. 2002.